SNVSBY3A
November 2020 – April 2021
TLV840-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Timing Diagrams
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Input Voltage (VDD)
8.3.1.1
VDD Hysteresis
8.3.1.2
VDD Transient Immunity
8.3.2
User-Programmable Reset Time Delay
8.3.3
Manual Reset (MR) Input
8.3.4
Output Logic
8.3.4.1
RESET Output, Active-Low
8.3.4.2
RESET Output, Active-High
8.4
Device Functional Modes
8.4.1
Normal Operation (VDD > VPOR)
8.4.2
Below Power-On-Reset (VDD < VPOR)
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design 1: Dual Rail Monitoring with Power-up Sequencing
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Application Curve: Adjusting Output Reset Delay on TLV840EVM
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Nomenclature
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DBV|5
MPDS018T
サーマルパッド・メカニカル・データ
発注情報
snvsby3a_oa
snvsby3a_pm
9.2.1.3
Application Curves
Figure 9-2
Startup Sequence Highlighting the Delay Between 3.3 V and 1.2 V Rails