SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

At 0.7 V ≤ VDD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage TLV840MAxL 0.7 6 V
VIT– Negative-going input threshold accuracy (1) VIT- = 0.8 V to 1.7 V –2.5 ±0.5 2.5 %
VIT- = 1.8 V to 5.4 V –2 ±0.5 2
VHYS Hysteresis on VIT– pin 2.5 5 7 %
IDD Supply current into VDD pin (2) VDD = 2 V; VIT– = 0.8 V to 1.8 V 0.12 1.0 µA
VDD = 6 V; VIT– = 0.8 V to 5.4 V 0.15 1.2
V MR_L Manual reset logic low input (2) 0.3VDD V
V MR_H Manual reset logic high input (2) 0.7VDD V
R MR Manual reset internal pull-up resistance 100 kΩ
RCT CT pin internal resistance 500 kΩ
TLV840MADL (Open-drain active-low)
VPOR Power on Reset Voltage (3) VOL(max) = 300 mV
IOUT(Sink) = 15 µA		 700 mV
VOL Low level output voltage
 		 VDD = 0.7 V, 0.8 V ≤ VIT–  ≤ 1.5 V
IOUT(Sink) = 15 µA		 300 mV
VDD =1.5 V, 1.6 V ≤ VIT– ≤ 3.3 V
IOUT(Sink) = 500 µA		 300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 V
IOUT(Sink) = 2 mA		 300
Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6V
TA = –40℃ to 85℃		 10 100 nA
VDD = VPULLUP = 6V 10 350 nA
TLV840MAPL (Push-pull active-low)
VPOR Power on Reset Voltage (3) VOL(max) = 300 mV
IOUT(Sink) = 15 µA		 700 mV
VOL Low level output voltage
 		 VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 V
IOUT(Sink) = 15 µA		 300 mV
VDD = 1.5 V, 1.6 V ≤ VIT– ≤ 3.3 V
IOUT(Sink) = 500 µA		 300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 V
IOUT(Sink) = 2 mA		 300
VOH High level output voltage
 		 VDD = 1.8 V, 0.8 V ≤ VIT– ≤ 1.4 V
IOUT(Source) = 500 µA		 0.8VDD V
VDD = 3.3 V, 1.5 V ≤ VIT– ≤ 3.0 V
IOUT(Source) = 500 µA		 0.8VDD
VDD = 6 V, 3.1 V ≤ VIT– ≤ 5.5 V
IOUT(Source) = 2 mA		 0.8VDD
TLV840MAPH (Push-pull active-high)
VPOR Power on Reset Voltage (3) VOH(min) = 0.8VDD V
IOUT (Source) = 15 uA		 900 mV
VOL Low level output voltage
 		 VDD=3.3 V
0.8 V ≤ VIT- ≤ 3.0 V
IOUT(Sink) = 500 µA		 300 mV
VDD=6 V
3.1 V ≤ VIT- ≤ 5.5 V
IOUT(Sink) = 2 mA		 300 mV
VOH High level output voltage
 		 VDD = 0.9 V 
1 V ≤ VIT- ≤ 1.5 V
IOUT(Sink) = 15 µA		 0.8VDD V
VDD=1.5 V
1.6 V ≤ VIT- ≤ 3.3 V
IOUT(Sink) = 500 µA		 0.8VDD V
VDD=3.3 V
3.4 V ≤ VIT- ≤ 5.5 V
IOUT(Sink) = 2 mA		 0.8VDD V
(1) VIT– threshold voltage range from 0.8 V to 5.4 V (for DL, PL versions) in 100 mV steps
(2) If the logic signal driving MR  is less than VDD, then IDD current increases based on voltage differential
(3) VPOR is the minimum VDD voltage level for a controlled output state