SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Timing Requirements

At 0.7 V ≤ VDD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tP_HL Propagation detect delay for VDD falling below VIT– VDD : (VIT+ + 10%) to (VIT– – 10%)(1) 30 50 µs
tD Reset time delay CT pin = Open or NC
(VIT- - 10%) to (VIT+ + 10%)		 40 80 µs
CT pin = 10 nF 6.2 ms
CT pin = 1 µF 619 ms
tGI_VIT– Glitch immunity VIT– 5% VIT– overdrive(2) 10 µs
tSTRT Startup Delay (3) CT pin = Open or NC
 		 300 µs
t MR_PW MR pin pulse duration to assert reset (4) 500 ns
t MR_RES Propagation delay from MR low to reset assertion VDD = 3.3 V,
MR = V MR_H to V MR_L  		1 µs
t MR_tD Delay from MR  release to reset deassert VDD = 3.3 V,
MR = V MR_L to V MR_H   		tD ms
(1) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
(2) Overdrive % = [(VDD/ VIT–) – 1] × 100%
(3) When VDD starts from less than the specified minimum VDD and then exceeds VIT-, reset is release after the startup delay (tSTRT), a capacitor at CT pin will add tD delay to tSTRT time
(4) Refer section on Manual Reset Input for min pulse width needed on MR pin