JAJSJ16G May   2020  – March 2024 TLV9151-Q1 , TLV9152-Q1 , TLV9154-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 EMI Rejection
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Capacitive Load and Stability
      4. 6.3.4 Common-Mode Voltage Range
      5. 6.3.5 Phase Reversal Protection
      6. 6.3.6 Electrical Overstress
      7. 6.3.7 Overload Recovery
      8. 6.3.8 Typical Specifications and Distributions
      9. 6.3.9 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
        2. 8.1.1.2 TI Precision Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5.     Trademarks
    6. 8.5 静電気放電に関する注意事項
    7. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.3 Capacitive Load and Stability

The TLV915x-Q1 features a resistive output stage capable of driving moderate capacitive loads, and by leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 6-3 and Figure 6-4. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation.

GUID-AF5CC63E-9D86-4D2A-8FF6-85160916960A-low.gifFigure 6-3 Small-Signal Overshoot vs Capacitive Load (10-mV Output Step, G = 1)
GUID-585EE4AB-C300-42BA-B4AB-88BDB33E3602-low.gifFigure 6-4 Small-Signal Overshoot vs Capacitive Load (10-mV Output Step, G = –1)

For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small resistor, RISO, in series with the output, as shown in Figure 6-5. This resistor significantly reduces ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. The high capacitive load drive of the TLV915x-Q1 is designed for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 6-5 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin.

GUID-F8F811CA-A43E-4F50-93BD-80FC7AF22FAA-low.gifFigure 6-5 Extending Capacitive Load Drive With the TLV9151-Q1