JAJSOZ7A August 2022 – April 2024 TMDS1204
PRODUCTION DATA
Table 7-18 and Table 7-19 lists how the SCL/CFG0 and the SDA/CFG1 pins will be used to control the HDMI 1.4 termination, lane SWAP function, and the DisplayPort mode in pin-strap mode.
SCL/CFG0 Pin | AC_EN Pin | TMDS1204 Function |
---|---|---|
0 | 0 | HDMI 1.4 termination is open if HDMI clock frequency ≤ fHDMI14_open |
0 | 0 | HDMI 1.4 termination is ≅300Ω if HDMI clock frequency ≥ fHDMI14_300 |
1 | 0 | HDMI 1.4 termination is ≅300Ω |
0 | 1 | Normal HDMI. Function determined by MODE pin. |
1 | 1 | DisplayPort mode. DDC snoop disabled. All four lanes enabled when HPD_IN is high. 12Gbps CTLE used. |
SDA/CFG1 Pin | TMDS1204 Function |
---|---|
0 | Normal Lane ordering |
1 | Lane Swap enabled |
The SCL/CFG0 is the only two-level pin that is continuously sampled in pin-strap mode. AC_EN, HPDOUT_SEL, and SDA/CFG1 will not be continuously sampled in pin-strap mode unless indicated otherwise.
The TMDS1204 must be configured as a linear redriver when operating in DisplayPort mode.