SLASE75D August 2015 – September 2017 TMDS181
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VCC | 13, 43 | P | 3.3 V power supply |
VDD | 14, 23, 24, 37, 48 | P | 1.2 V power supply |
GND | 7, 19, 41, 30, Thermal pad |
G | Ground |
MAIN LINK INPUT PINS | |||
IN_D2p/n | 2, 3 | I | Channel 2 differential input |
IN_D1p/n | 5, 6 | I | Channel 1 differential input |
IN_D0p/n | 8, 9 | I | Channel 0 differential input |
IN_CLKp/n | 11, 12 | I | Clock differential input |
MAIN LINK OUTPUT PINS (FAIL SAFE) | |||
OUT_D2n/p | 34, 35 | O | TMDS data 2 differential output |
OUT_D1n/p | 31, 32 | O | TMDS data 1 differential output |
OUT_D0n/p | 28, 29 | O | TMDS data 0 differential output |
OUT_CLKn/p | 25, 26 | O | TMDS data clock differential output |
HOT PLUG DETECT PINS | |||
HPD_SRC | 4 | O | Hot plug detect output to source side |
HPD_SNK | 33 | I | Hot plug detect input from sink side |
AUDIO RETURN CHANNEL AND DDC PINS | |||
SPDIF_IN ARC_OUT |
45 44 |
I/O | SPDIF signal input Audio return channel output |
SDA_SRC SCL_SRC |
47 46 |
I/O | Source side TMDS port bidirectional DDC data line Source side TMDS port bidirectional DDC clock line |
SDA_SNK SCL_SNK |
39 38 |
I/O | Sink side TMDS port bidirectional DDC data line Sink side TMDS port bidirectional DDC clock line |
CONTROL PINS | |||
OE | 42 | I | Operation enable/reset pin OE = L: Power-down mode OE = H: Normal operation Internal weak pull up: Resets device when transitions from H to L |
SIG_EN | 17 | I | Signal detector circuit enable SIG_EN = L: Signal detect circuit disabled: SIG_EN = H: Signal detect circuit enabled: When no valid clock device enters standby mode. Internal weak pull down |
PRE_SEL | 20 | I 3 level |
De-emphasis control when I2C_EN/PIN = Low. PRE_SEL = L: –2 dB PRE_SEL = No Connect: 0 dB PRE_SEL = H: Reserved When I2C_EN/PIN = High de-emphasis is controlled through I2C |
EQ_SEL/A0 | 21 | I 3 level |
Input receive equalization pin strap when I2C_EN/PIN = Low EQ_SEL = L: Fixed EQ at 7.5 dB at 3 GHz EQ_SEL = No Connect: Adaptive EQ EQ_SEL = H: Fixed at 14 dB at 3 GHz When I2C_EN/PIN = High address bit 1 Note: 3 level for pin strap programming but 2 level when I2C address |
I2C_EN/PIN | 10 | I | I2C_EN/PIN = High; puts device into I2C Control Mode I2C_EN/PIN = Low; puts device into pin strap mode Note: I2C CSR is addressable at all times, but features that can be controlled by pin strapping can only be changed by I2C when this pin is pulled high |
SCL_CTL | 15 | I | I2C clock signal Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C |
SDA_CTL | 16 | I/0 | I2C data signal Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C |
VSadj | 22 | I | TMDS-compliant voltage swing control nominal resistor to GND |
A1 | 27 | I | High address bit 2 for I2C programming Weak internal pull down Note: When in Pin Strapping Mode leave pin as No connect |
TX_TERM_CTL | 36 | I 3 level |
Transmit termination control TX_TERM_CTL = H, no transmit termination TX_TERM_CTL = L, transmit termination impedance in approximately 75 to 150 Ω TX_TERM_CTL = No Connect, automatically selects the termination impedance Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination 2 Gbps > DR < 3.4 Gbps – 150 to 300 Ω differential near end termination DR < 2 Gbps – no termination Note: If left floating will be in automatic select mode. |
SWAP/POL | 1 | I 3 level |
Input lane SWAP and polarity control pin SWAP/POL = H: receive lanes polarity swap (retimer mode only) SWAP/POL = L: receive lanes swap (redriver and retimer mode) SWAP/POL = No Connect: normal operation |
NC | 18, 40 | NA | No connect |