SLASE75D August   2015  – September 2017 TMDS181

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Electrical Characteristics
    6. 6.6  TMDS Differential Input Electrical Characteristics
    7. 6.7  TMDS Differential Output Electrical Characteristics
    8. 6.8  DDC, I2C, HPD, and ARC Electrical Characteristics
    9. 6.9  Power-Up and Operation Timing Requirements
    10. 6.10 TMDS Switching Characteristics
    11. 6.11 HPD Switching Characteristics
    12. 6.12 DDC and I2C Switching Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Training for HDMI2.0a Data Rate Monitor
      4. 8.4.4 DDC Functional Description
      5. 8.4.5 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 Local I2C Overview
      2. 8.5.2 Local I2C Control Bit Access TAG Convention
      3. 8.5.3 CSR Bit Field Definitions
        1. 8.5.3.1 ID Registers
        2. 8.5.3.2 MISC CONTROL Register
        3. 8.5.3.3 Equalization Control Register
        4. 8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Source Side Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sink Side Application
      3. 9.2.3 Application Chain Showing DDC Connections
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 DDC Pullup Resistors
          2. 9.2.3.1.2 Compliance Testing
            1. 9.2.3.1.2.1 Pin Strapping Configuration for HDMI2.0a and HDMI1.4b
            2. 9.2.3.1.2.2 I2C Control for HDMI2.0a and HDMI1.4b
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Supply voltage(3) VCC –0.3 4 V
VDD –0.3 1.4
Voltage Main link input differential voltage (IN_Dx, IN_CLKx) IIN = 15mA VCC - 0.75V VCC + 0.3V V
TMDS outputs ( OUT_Dx) –0.3 4
HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL, –0.3 4
HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC –0.3 6
Input Current IIN Main link input current (IN_Dx, IN_CLKx) 15 mA
Continuous power dissipation See Thermal Information
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage nominal value 3.3 V 3.135 3.3 3.465 V
VDD Supply voltage nominal value 1.2 V 1.1 1.2 1.27 V
TCASE Case temperature 92.7 °C
TA Operating free-air temperature TMDS181 0 85 °C
TMDS181I –40 85 °C
MAIN LINK DIFFERENTIAL PINS
VID_PP Peak-to-peak input differential voltage 75 1560 mVpp
VIC Input common mode voltage VCC – 0.4 VCC + 0.1 V
dR Data rate 0.25 6 Gbps
RVSADJ TMDS compliant swing voltage bias resistor nominal 4.5 7.06 kΩ
CONTROL PINS
VI-DC DC input voltage Control pins –0.3 3.6 V
VIL(1) Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only 0.3 V
Low-level input voltage at OE 0.8
VIM(1) Mid-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only 1 1.2 1.4 V
VIH(1) High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE(2) pins only 2.6 V
VOL Low-level output voltage 0.4 V
VOH High-level output voltage 2.4 V
IIH High-level input current –30 30 µA
IIL Low-level input current –25 25 µA
IOS Short-circuit output current –50 50 mA
IOZ High impedance output current 10 µA
ROEPU Pullup resistance on OE pin 150 250 kΩ
(1) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the internal bias to the proper voltage level which will not match the values shown here.
(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.4 Thermal Information

THERMAL METRIC(1)(2) TMDS181x UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 31.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.2 °C/W
RθJB Junction-to-board thermal resistance 8.1 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 8.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Test conditions for ΨJB and ΨJT are clarified in the Semiconductor and IC Package Thermal Metrics.

6.5 Power Supply Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX(1) UNIT
PD1(3)(4) Device power dissipation
(retimer operation)		 OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern, VI = 3.3 V, I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= NC, SDA_CTL/CLK_CTL = 0 V		 800 900 mW
PD2(3)(4) Device power dissipation
(redriver operation)		 OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 2.97 Gbps TMDS pattern, VI = 3.3 V, I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= H, SDA_CTL/CLK_CTL = 0 V		 500 600 mW
PSD1(3)(4)(5) Device power in standby OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V, HPD = H, No valid input signal 50 100 mW
PSD2(3)(4)(5) Device power in power down OE = L, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V 10 30 mW
ICC1(3)(4) VCC supply current (TMDS 6Gpbs retimer mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC, SDA_CTL/CLK_CTL = 0 V		 131 150 mA
IDD1(3)(4) VDD supply current (TMDS 6Gpbs retimer mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC, SDA_CTL/CLK_CTL = 0 V		 332 350 mA
ICC2(3)(4) VCC supply current (TMDS 6Gpbs redriver mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 2.97 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V		 92 mA
IDD2(3)(4) VDD supply current (TMDS 6Gpbs redriver mode) OE = H, VCC= 3.3 V/3.465 V, VDD = 1.2 V/1.27 V
IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern
I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V		 187 mA
ISD1(5) Standby current OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V, HPD = H: No valid signal on IN_CLK 3.3 V rail(3) 6 15 mA
1.2 V rail 40 50
ISD2(5) Power-down current OE = L, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V 3.3 V rail(3) 2 5 mA
1.2 V rail 3.5 15
(1) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted
(2) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature unless otherwise noted
(3) ICC is a direct result of the source design as the TMDS181x integrated receive termination resistor accounts for 85 to 110 mA.
(4) IDD is impacted by ARC usage. Connecting a 500 kΩ resistor to GND at SPDIF reduces the value by more than 20 mA
(5) The measurements were made with no active source connected.

6.6 TMDS Differential Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX(1) UNIT
DR_RX_DATA_RT TMDS data lanes data rate (Retimer Mode) 0.25 6 Gbps
DR_RX_DATA_RD TMDS data lanes data rate (Redriver Mode) 0.25 3.4 Gbps
DR_RX_CLK TMDS clock lanes clock rate 25 340 MHz
tRX_DUTY Input clock duty circle 40% 50% 60%
tCLK_JIT Input clock jitter tolerance 0.3 Tbit
tDATA_JIT Input data jitter tolerance Test the TTP2, see Figure 12 150 ps
tRX_INTRA Input intrapair skew tolerance Test at TTP2 when DR = 1.6 Gbps, see Figure 12 112 ps
tRX_INTER Input interpair skew tolerance 1.8 ns
EQH(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = H; fixed EQ gain, test at 6 Gbps 15 dB
EQL(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = L; fixed EQ gain, test at 6 Gbps 7.5 dB
EQZ(D) Adaptive EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = NC; adaptive EQ (Retimer Mode Only) 2 15 dB
EQ(c) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0 = H,L,NC 3 dB
RINT Input differential termination impedance 85 100 115 Ω
VITERM Input termination voltage OE = H 3.3 3.465 V
(1) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
(2) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

6.7 TMDS Differential Output Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX(1) UNIT
VOH Single-ended high level output voltage
Data rate ≤1.65 Gbps		 PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ; VCC – 10 VCC + 10 V
Single-ended high level output voltage
Data rate >1.65 Gbps and <3.4 Gbps		 PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ; VCC-200 VCC + 10
Single-ended high level output voltage
Data rate >3.4 Gbps and < 6 Gbps(1)		 PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ; VCC – 400 VCC + 10
VOL Single-ended low level output voltage
Data rate ≤1.65 Gbps		 PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ; VCC – 600 VCC – 400 V
Single-ended low level output voltage
Data rate >1.65 Gbps and <3.4 Gbps		 PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ; VCC – 700 VCC – 400
Single-ended low level output voltage
Data rate >3.4 Gbps and < 6 Gbps(1)		 PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ; VCC – 1000 VCC – 400
VSWING_DA Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC/L; OE = H; DR = 270 Mbps/2.97/6 Gbps VSadj = 7.06 kΩ; 400 500 600 mV
VSWING_CLK Single-ended output voltage swing on clock lane PRE_SEL = NC; TX_TERM_CTL = H; OE = H; Data rate ≤ 3.4 Gbps; VSadj = 7.06 kΩ; 400 500 600 mV
PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; Data rate > 3.4 Gbps; VSadj = 7.06 kΩ; 200 300 400
ΔVSWING Change in single-end output voltage swing per 100 Ω ΔVSadj 20 mV
ΔVOCM(SS) Change in steady state output common mode voltage between logic levels –5 5 mV
VOD(PP) Output differential voltage before pre-emphasis VSADJ = 7.06 kΩ; PRE_SEL = NC see Figure 10 800 1200 mV
VOD(SS) Steady state output differential voltage VSADJ = 7.06 kΩ; PRE_SEL = L, see Figure 11 600 1075 mV
VOD_range Total TMDS data lanes output differential voltage for HDMI2.0. Retimer Mode Only
See Figure 14		 3.4 Gbps < Rbit ≤ 3.712 Gps
TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ;		 335 mV
3.712 Gbps < Rbit < 5.94 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ;		 –19.66 × (Rbit2) + (106.74 × Rbit) + 209.58
5.94 Gbps ≤ Rbit ≤ 6.0 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ;		 150
IOS Short-circuit current limit Main link output shorted to GND 50 mA
ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3 V through 50 Ω resistor; 45 μA
RTERM Source termination resistance for HDMI2.0 75 150 Ω
(1) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
(2) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

6.8 DDC, I2C, HPD, and ARC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX(1) UNIT
DDC AND I2C
VI-DC SCL/SDA_SNK, SCL/SDA_SRC DC input voltage –0.3 5.5 V
SCL/SDA_CTL, DC input voltage –0.3 3.6 V
VIL SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V
SCL/SDA_CTL Low level input voltage 0.3 x VCC V
VIH SCL/SDA_SNK, SCL/SDA_SRC high level input voltage 3 V
SCL/SDA_CTL high level input voltage 0.7 x VCC V
VOL SCL/SDA_CTL, SCL/SDA_SRC low level output voltage I0 = 3 mA and VCC > 2 V 0.4 V
I0 = 3 mA and VCC < 2 V 0.2 x VCC
fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz
Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF
HPD
VIH High-level input voltage HPD_SNK 2.1 V
VIL Low-level input voltage HPD_SNK 0.8 V
VOH High-level output voltage IOH = –500 µA; HPD_SRC, 2.4 3.6 V
VOL Low-level output voltage IOL = 500 µA; HPD_SRC, 0 0.1 V
ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V; 40 μA
IH_HPD High-level input current Device powered; VIH = 5 V;
IH_HPD includes RpdHPD resistor current		 40 µA
Device powered; VIL = 0.8 V;
IL_HPD includes RpdHPD resistor current		 30
RpdHPD HPD input termination to GND VCC = 0 V 150 190 220 kΩ
SPDIF AND ARC
VEL Operating DC voltage for single mode ARC output Test at ARC_OUT, see Figure 22 0 5 V
VIN_DC Operating DC voltage for SPDIF input 0.05 V
VSP_SW Signal amplitude of SPDIF input 0.2 0.5 0.6 V
VElSWING Signal amplitude on the ARC output Test at ARC_OUT, 55 Ω external termination resistor, see Figure 22 0.4 0.5 0.6 V
CLK_ARC Signal frequency on ARC Test at ARC_OUT, see Figure 22 3.687 5.645 ±0.1% 13.517 MHz
Duty cycle Output clock duty cycle 45% 50% 55%
Data rate SPDIF input DR 7.373 11.29 27.034 Mbps
tEDGE Rise/fall time for ARC output From 10% to 90% voltage level 0.4 UI
R_IN_SPDIF Input termination resistance for SPDIF 75 Ω
Rest Single mode output termination resistance 0.1 MHz to 128× the maximum frame rate 36 55 75 Ω
(1) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
(2) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

6.9 Power-Up and Operation Timing Requirements

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
td1 VDD stable before VCC 0 200 µs
td2 VDD and VCC stable before OE assertion 100 µs
td3 CDR active operation after retimer mode initial 15 ms
td4 CDR turn off time after retimer mode de-assert 120 ns
VDD_ramp VDD supply ramp up requirements 100 ms
VCC_ramp VCC supply ramp up requirements 100 ms
(1) See Operation Timing for more information
TMDS181 TMDS181I Power_up_Timing_sllsen7.gif Figure 1. Power-Up Timing for TMDS181
TMDS181 TMDS181I CDR_Timing_sllsen7.gif Figure 2. CDR Timing for TMDS181

6.10 TMDS Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX(1) UNIT
REDRIVER MODE
dR Data rate (redriver mode) 250 3400 Mbps
tPLH Propagation delay time (low to high) 250 600 ps
tPHL Propagation delay time (high to low) 250 800 ps
tT1(1.4b) Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; 1.48 Gbps and 2.97 Gbps data lines, 148 MHz and 297 MHz clock 75 ps
tT3 TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; 1.48 Gbps, 2.97 Gbps 100 ps
tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps; See Figure 8 40 ps
tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps; See Figure 8 100 ps
tJITD1(1.4b) Total output data jitter HDMI1.4b DR = 2.97 Gbps, PRE_SEL = NC, EQ_SEL/A0 = NC ; . See Figure 12 at TTP3 0.2 Tbit
tJITC1(1.4b) Total output clock jitter CLK = 25 MHz, 74.25 MHz, 75 MHz, 150 MHz, 297 MHz 0.25 Tbit
RETIMER MODE
dR Data rate (retimer mode) 0.25 6 Gbps
dXVR Automatic redriver to retimer crossover (when selected) Measured with input signal applied = 200 mVpp 0.75 1 1.25 Gbps
fCROSSOVER Crossover frequency hysteresis 250 MHz
PLLBW Data retimer PLL bandwidth Default loop bandwidth setting 0.4 1 MHz
tACQ Input clock frequency detection and retimer acquisition time 180 µs
IJT1 Input clock jitter tolerance Tested when data rate >1.0Gbps 0.3 Tbit
tT1(2.0) Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. TX_TERM_CTL = L; PRE_SEL = NC; 6 Gbps data lines, 45 ps
tT1 (1.4b) TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps and 2.97 Gbps data lines, 148 MHz and 297 MHz clock 75 ps
tT3 TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock 100 ps
tDCD OUT_CLK ± duty cycle 40% 50% 60%
tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock; See Figure 8 0.2 Tch
tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock; See Figure 8 0.15 Tbit
tJITC1(1.4b) Total output clock jitter CLK = 25 MHz, 74.25 MHz, 75 MHz, 150 MHz, 297 MHz 0.25 Tbit
tJITC1(2.0) DR = 6 Gbps: CLK = 150 MHz 0.3 Tbit
tJITD2 Total output data jitter
See Figure 14		 3.4 Gbps < Rbit ≤ 3.712 Gps
TX_TERM_CTL = NC; PRE_SEL = NC; OE = H		 0.4 Tbit
3.712 Gbps < Rbit < 5.94 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC; OE = H		 –0.0332Rbit2 + 0.2312Rbit + 0.1998
5.94 Gbps ≤ Rbit ≤ 6.0 Gbps
TX_TERM_CTL = NC; PRE_SEL = NC; OE = H		 0.6
(1) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
(2) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

6.11 HPD Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX(1) UNIT
tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge(1) See Figure 16; not valid during switching time 40 120 ns
tT(HPD) HPD logical disconnected timeout See Figure 17 2 ms
(1) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted
(2) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

6.12 DDC and I2C Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Rise time of both SDA and SCL signals VCC = 3.3 V 300 ns
tf Fall time of both SDA and SCL signals 300 ns
tHIGH Pulse duration, SCL high 0.6 μs
tLOW Pulse duration, SCL low 1.3 μs
tSU1 Setup time, SDA to SCL 100 ns
tST, STA Setup time, SCL to start condition 0.6 μs
tHD,STA Hold time, start condition to SCL 0.6 μs
tST,STO Setup time, SCL to stop condition 0.6 μs
t(BUF) Bus free time between stop and start condition 1.3 μs
tPLH1 Propagation delay time, low-to-high-level output Source to sink: 100kbps pattern; Cb(Sink) = 400 pF(1); see Figure 20 360 ns
tPHL1 Propagation delay time, high-to-low-level output 230 ns
tPLH2 Propagation delay time, low-to-high-level output Sink to source: 100kbps pattern; Cb(Source) = 100 pF(1); see Figure 21 250 ns
tPHL2 Propagation delay time, high-to-low-level output 200 ns
(1) Cb = total capacitance of one bus line in pF.

6.13 Typical Characteristics

TMDS181 TMDS181I D001_SLASE75.gif
Figure 3. Current vs Data Rate Redriver Mode
TMDS181 TMDS181I D003_SLASE75.gif
Figure 5. VSADJ vs VOD
TMDS181 TMDS181I D002_SLASE75.gif
Figure 4. Current vs Data Rate Retimer Mode