JAJSOO4B September 2011 – June 2022 TMP100-Q1 , TMP101-Q1
PRODUCTION DATA
The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All targets on the bus shift in the target address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target being addressed responds to the controller by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer, SDA must remain stable while SCL is HIGH because any change in SDA while SCL is HIGH is interpreted as a control signal.
When all data are transferred, the controller generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH.