The TMP75-Q1 and TMP175-Q1 devices are digital temperature sensors ideal for negative temperature coefficient (NTC) and positive temperature coefficient (PTC) thermistor replacement. The devices offer a typical accuracy of ±1°C without requiring calibration or external component signal conditioning. Device temperature sensors are highly linear and do not require complex calculations or look-up tables to derive the temperature. The on-chip, 12-bit, analog-to-digital converter (ADC) offers resolutions down to 0.0625°C. The devices are available in the industry-standard, LM75, 8-pin SOIC and VSSOP footprint.
The TMP175-Q1 and TMP75-Q1 feature SMBus, two-wire, and I2C interface compatibility. The TMP175-Q1 device allows up to 27 devices on one bus. The TMP75-Q1 allows up to eight devices on one bus. The TMP175-Q1 and TMP75-Q1 both feature an SMBus alert function.
The TMP175-Q1 and TMP75-Q1 devices are ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The TMP75-Q1 production units are 100% tested against sensors that are NIST-traceable and are verified with equipment that are NIST-traceable through ISO/IEC 17025 accredited calibrations.
The TMP175-Q1 and TMP75-Q1 devices are specified for operation over the temperature range of –40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TMPx75-Q1 | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm |
DATE | REVISION | NOTES |
---|---|---|
November 2015 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | SDA | I/O | Serial data. Open-drain output; requires a pullup resistor. |
2 | SCL | I | Serial clock. Open-drain output; requires a pullup resistor. |
3 | ALERT | O | Overtemperature alert. Open-drain output; requires a pullup resistor. |
4 | GND | — | Ground |
5 | A2 | I | Address select. Connect to GND, V+, or (for the TMP175-Q1 device only) leave these pins floating. |
6 | A1 | ||
7 | A0 | ||
8 | V+ | I | Supply voltage, 2.7 V to 5.5 V |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power supply, V+ | 7 | V | ||
Input voltage(2) | –0.5 | 7 | V | |
Input current | 10 | mA | ||
Operating temperature | –55 | 127 | °C | |
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –60 | 130 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Supply voltage | 2.7 | 5.5 | V | |
Operating free-air temperature, TA | –40 | 125 | °C |
THERMAL METRIC(1) | TMP175-Q1, TMP75-Q1 | UNIT | |
---|---|---|---|
DGK (SOIC), D (VSSOP) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 185 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 76.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 106.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 14.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 104.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
TEMPERATURE INPUT | ||||||||
Range | –40 | 125 | °C | |||||
Accuracy (temperature error) | –25°C to +85°C | TMP175-Q1 | ±0.5 | ±1.5 | °C | |||
TMP75-Q1 | ±0.5 | ±2 | ||||||
–40°C to +125°C | TMP175-Q1 | ±1 | ±2 | |||||
TMP75-Q1 | ±1 | ±3 | ||||||
Accuracy (temperature error) vs supply | 0.2 | ±0.5 | °C/V | |||||
Resolution(1) | Selectable | 0.0625 | °C | |||||
DIGITAL INPUT/OUTPUT | ||||||||
Input capacitance | 3 | pF | ||||||
VIH | High-level input logic | 0.7 (V+) | 6 | V | ||||
VIL | Low-level input logic | –0.5 | 0.3 (V+) | V | ||||
IIN | Leakage input current | 0 V ≤ VIN ≤ 6 V | 1 | µA | ||||
Input voltage hysteresis | SCL and SDA pins | 500 | mV | |||||
VOL | Low-level output logic | SDA | IOL = 3 mA | 0 | 0.15 | 0.4 | V | |
ALERT | IOL = 4 mA | 0 | 0.15 | 0.4 | ||||
Resolution | Selectable | 9 to 12 | Bits | |||||
Conversion time | 9 bits | 27.5 | 37.5 | ms | ||||
10 bits | 55 | 75 | ||||||
11 bits | 110 | 150 | ||||||
12 bits | 220 | 300 | ||||||
Timeout time | 25 | 54 | 74 | ms | ||||
POWER SUPPLY | ||||||||
Operating range | 2.7 | 5.5 | V | |||||
IQ | Quiescent current | Serial bus inactive | 50 | 85 | µA | |||
Serial bus active, SCL frequency = 400 kHz | 100 | |||||||
Serial bus active, SCL frequency = 3.4 MHz | 410 | |||||||
ISD | Shutdown current | Serial bus inactive | 0.1 | 3 | µA | |||
Serial bus active, SCL frequency = 400 kHz | 60 | |||||||
Serial bus active, SCL frequency = 3.4 MHz | 380 | |||||||
TEMPERATURE RANGE | ||||||||
Specified range | –40 | 125 | °C | |||||
Operating range | –55 | 127 | °C |
FAST MODE | HIGH-SPEED MODE | UNIT | |||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
ƒ(SCL) | SCL operating frequency | V+ | 0.001 | 0.4 | 0.001 | 2.38 | MHz |
t(BUF) | Bus-free time between STOP and START condition | See the Timing Diagrams section | 1300 | 160 | ns | ||
t(HDSTA) | Hold time after repeated START condition. After this period, the first clock is generated. |
600 | 160 | ns | |||
t(SUSTA) | Repeated START condition setup time | 600 | 160 | ns | |||
t(SUSTO) | STOP condition setup time | 600 | 160 | ns | |||
t(HDDAT) | Data hold time | 4 | 900 | 4 | 120 | ns | |
t(SUDAT) | Data setup time | 100 | 10 | ns | |||
t(LOW) | SCL clock low period | V+ , see the Timing Diagrams section | 1300 | 280 | ns | ||
t(HIGH) | SCL clock high period | See the Timing Diagrams section | 600 | 60 | ns | ||
tFD | Data fall time | See the Timing Diagrams section | 300 | 150 | ns | ||
tRC | Clock rise time | See the Two-Wire Timing Diagrams section | 300 | 40 | ns | ||
SCLK ≤ 100 kHz, see the Timing Diagrams section | 1000 | ns | |||||
tFC | Clock fall time | See the Two-Wire Timing Diagrams section | 300 | 40 | ns |
Serial bus inactive | ||
12-bit resolution | ||
3 typical units, 12-bit resolution | ||