2 Revision History
Changes from May 30, 2016 to October 31, 2019 (from C Revision () to D Revision)
- Section 1.1 (Features): Updated/Changed Addressable Memory Space from "8" to "4" GBGo
- Section 1.1: Added "Up to" to the Eight 64-Bit Timers bulletGo
- Figure 4-3 (Upper Left Quadrant — A): Updated/Changed the pin function name on ball AD13 from "RSV28" to "SGMIICLKP"Go
- Figure 4-4 (Upper Right Quadrant — B): Updated/Changed the pin function names on balls AE14, AD20, W21, and V21Go
- Table 5-25 (McBSP Switching Characteristics): Added associated "CLKRP = CLKXP = FSRP = FSXP = 0 ..." footnoteGo
- Section 6.18 (Multichannel Buffered Serial Port (McBSP)): Added new paragraph on GPIO option not supported Go
- Table 6-63 (Memory Map Summary): Updated/Changed the LOGICAL and PHYSICAL ending address locations from "0C1FFFFF" to "0C0FFFFF"Go
- Table 6-63: Updated/Changed the extended DDR3 memory space access specified in the footnote from "8" to "4" GBGo
- Table 6-68 (EMIF16 Boot Configuration Field Descriptions): Added "(Default)" to the 0 = CS2 option of the Chip Select field Go
- Table 6-68: Added a Note to the Chip Select DescriptionGo
- Table 6-74 (I2C Master Mode Device Configuration Field Descriptions): Updated/Changed the Parameter Index field value range from "0 to 31" to "0 to 63" in the DescriptionGo
- Table 6-76 (SPI Device Configuration Field Descriptions): Updated/Changed the Description for the Chip Select fieldGo
- Table 6-76: Updated/Changed the Description for the Parameter Table Index fieldGo
- Table 6-78 (Boot Parameter Table Common Values): Added additional text to Description of the Checksum fieldGo
- Section 7.1.4 (MSM SRAM): Updated/Changed the extension of external addresses bullet from "... up to 8GB" to "... up to 4GB"Go
- Table 8-1 (C665x Device Configuration Pins): Updated/Changed the BOOTMODE[12:0] PIN NO. from "R3" to "R23"Go
- Figure 8-1 (Device Status Register): Added associated Legend footnote reference to "x" definitionGo