2 Revision History
Changes from February 1, 2014 to March 17, 2015 (from E Revision (February 2014) to F Revision)
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Updated entire document to adhere to Superior Data Manual StandardsGo
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Updated/Changed title from "...Video Processors..." to "...Digital Media Processors..."Go
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Updated/Changed ARM®Cortex™-A8 RISC Processor in Features from "Up to 1.35 GHz" to "Up to 1.20 GHz"Go
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Updated/Changed C674x™ VLIW DSP in Features from "Up to 1.25 GHz" to "Up to 1 GHz"Go
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Updated/Changed C674x™ VLIW DSP in Features from "Up to 9000 MIPS and 6750 MFLOPS" to "Up to 8000 MIPS and 6000 MFLOPS"Go
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Updated/Changed CPU Frequency row Go
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Removed Cycle Time row Go
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Updated/Changed Handling Ratings to ESD Ratings Go
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Updated/Changed CVDD Initial Startup NOM from "1.00 or 1.10" to "1.00 or 1.05" Go
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Updated/Changed CVDD CYG & CYG2 NOM from "0.85-1.10" top "0.85-1.05" Go
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Added footnote to CVDD CYG & CYG2 NOM valueGo
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Updated footnote from "1.10V nominal (for CYG..." to "1.05 nominal (for CYG..."Go
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Removed FSYSCLK row Go
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Removed "AVS Variable Core voltage = 0.8 V" from ICDO and IDDDGo
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Updated/Changed the System Clocking Overview Figure from "432 MHz" to "audio reference clock"Go
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Updated/Changed body of text in PLL Programming Limits Go
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Completely updated PLL Clock Frequencies tableGo
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Completely updated SYSCLK Frequencies tableGo
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Completely updated SYSCLK Frequencies tableGo
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Updated/Changed tsu(CMDV-CLKH) and th(CLKH-DATV) MIN from "6.0" to "4.1"Go
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Updated/Changed th(CLKH-CMDIV) and th(CLKH-DATV) MIN from "19.2" to "1.9"Go
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Added footnote to td(CLKL-CMD) and td(CLKL-DAT) MIN valuesGo
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Updated/Changed the blank example from "1.0-GHz ARM, 800-MHz DSP" to "930-MHz ARM, 750-MHz DSP"Go
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Updated DEVICE SPEED RANGE in Figure 10-1Go
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Completely updated Table 10-1Go