SPNS253A May   2018  – September 2019 TMS570LC4357-EP

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 GWT BGA Package Ball-Map (337 Terminal Grid Array)
    2. 3.2 Terminal Functions
      1. 3.2.1 GWT Package
        1. 3.2.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 3.2.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 3.2.1.3  RAM Trace Port (RTP)
        4. 3.2.1.4  Enhanced Capture Modules (eCAP)
        5. 3.2.1.5  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        6. 3.2.1.6  Enhanced Pulse-Width Modulator Modules (ePWM)
        7. 3.2.1.7  Data Modification Module (DMM)
        8. 3.2.1.8  General-Purpose Input / Output (GIO)
        9. 3.2.1.9  FlexRay Interface Controller (FlexRay)
        10. 3.2.1.10 Controller Area Network Controllers (DCAN)
        11. 3.2.1.11 Local Interconnect Network Interface Module (LIN)
        12. 3.2.1.12 Standard Serial Communication Interface (SCI)
        13. 3.2.1.13 Inter-Integrated Circuit Interface Module (I2C)
        14. 3.2.1.14 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        15. 3.2.1.15 Ethernet Controller
        16. 3.2.1.16 External Memory Interface (EMIF)
        17. 3.2.1.17 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)
        18. 3.2.1.18 System Module Interface
        19. 3.2.1.19 Clock Inputs and Outputs
        20. 3.2.1.20 Test and Debug Modules Interface
        21. 3.2.1.21 Flash Supply and Test Pads
        22. 3.2.1.22 Supply for Core Logic: 1.2-V Nominal
        23. 3.2.1.23 Supply for I/O Cells: 3.3-V Nominal
        24. 3.2.1.24 Ground Reference for All Supplies Except VCCAD
        25. 3.2.1.25 Other Supplies
      2. 3.2.2 Multiplexing
        1. 3.2.2.1 Output Multiplexing
          1. 3.2.2.1.1 Notes on Output Multiplexing
        2. 3.2.2.2 Input Multiplexing
          1. 3.2.2.2.1 Notes on Input Multiplexing
          2. 3.2.2.2.2 General Rules for Multiplexing Control Registers
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Power-On Hours (POH)
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 4.6  Wait States Required - L2 Memories
    7. 4.7  Power Consumption Summary
    8. 4.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 4.9  Thermal Resistance Characteristics for the BGA Package (GWT)
    10. 4.10 Timing and Switching Characteristics
      1. 4.10.1 Input Timings
      2. 4.10.2 Output Timings
  5. 5 System Information and Electrical Specifications
    1. 5.1  Device Power Domains
    2. 5.2  Voltage Monitor Characteristics
      1. 5.2.1 Important Considerations
      2. 5.2.2 Voltage Monitor Operation
      3. 5.2.3 Supply Filtering
    3. 5.3  Power Sequencing and Power-On Reset
      1. 5.3.1 Power-Up Sequence
      2. 5.3.2 Power-Down Sequence
      3. 5.3.3 Power-On Reset: nPORRST
        1. 5.3.3.1 nPORRST Electrical and Timing Requirements
    4. 5.4  Warm Reset (nRST)
      1. 5.4.1 Causes of Warm Reset
      2. 5.4.2 nRST Timing Requirements
    5. 5.5  ARM Cortex-R5F CPU Information
      1. 5.5.1 Summary of ARM Cortex-R5F CPU Features
      2. 5.5.2 Dual Core Implementation
      3. 5.5.3 Duplicate Clock Tree After GCLK
      4. 5.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety
        1. 5.5.4.1 Signal Compare Operating Modes
          1. 5.5.4.1.1 Active Compare Lockstep Mode
          2. 5.5.4.1.2 Self-Test Mode
          3. 5.5.4.1.3 Error Forcing Mode
          4. 5.5.4.1.4 Self-Test Error Forcing Mode
        2. 5.5.4.2 Bus Inactivity Monitor
        3. 5.5.4.3 CPU Registers Initialization
      5. 5.5.5 CPU Self-Test
        1. 5.5.5.1 Application Sequence for CPU Self-Test
        2. 5.5.5.2 CPU Self-Test Clock Configuration
        3. 5.5.5.3 CPU Self-Test Coverage
      6. 5.5.6 N2HET STC / LBIST Self-Test Coverage
    6. 5.6  Clocks
      1. 5.6.1 Clock Sources
        1. 5.6.1.1 Main Oscillator
          1. 5.6.1.1.1 Timing Requirements for Main Oscillator
        2. 5.6.1.2 Low-Power Oscillator
          1. 5.6.1.2.1 Features
          2. 5.6.1.2.2 LPO Electrical and Timing Specifications
        3. 5.6.1.3 Phase-Locked Loop (PLL) Clock Modules
          1. 5.6.1.3.1 Block Diagram
          2. 5.6.1.3.2 PLL Timing Specifications
        4. 5.6.1.4 External Clock Inputs
      2. 5.6.2 Clock Domains
        1. 5.6.2.1 Clock Domain Descriptions
        2. 5.6.2.2 Mapping of Clock Domains to Device Modules
      3. 5.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      4. 5.6.4 Clock Test Mode
    7. 5.7  Clock Monitoring
      1. 5.7.1 Clock Monitor Timings
      2. 5.7.2 External Clock (ECLK) Output Functionality
      3. 5.7.3 Dual Clock Comparators
        1. 5.7.3.1 Features
        2. 5.7.3.2 Mapping of DCC Clock Source Inputs
    8. 5.8  Glitch Filters
    9. 5.9  Device Memory Map
      1. 5.9.1 Memory Map Diagram
      2. 5.9.2 Memory Map Table
      3. 5.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 5.9.4 Master/Slave Access Privileges
        1. 5.9.4.1 Special Notes on Accesses to Certain Slaves
      5. 5.9.5 MasterID to PCRx
      6. 5.9.6 CPU Interconnect Subsystem SDC MMR Port
      7. 5.9.7 Parameter Overlay Module (POM) Considerations
    10. 5.10 Flash Memory
      1. 5.10.1 Flash Memory Configuration
      2. 5.10.2 Main Features of Flash Module
      3. 5.10.3 ECC Protection for Flash Accesses
      4. 5.10.4 Flash Access Speeds
      5. 5.10.5 Flash Program and Erase Timings
        1. 5.10.5.1 Flash Program and Erase Timings for Program Flash
        2. 5.10.5.2 Flash Program and Erase Timings for Data Flash
    11. 5.11 L2RAMW (Level 2 RAM Interface Module)
      1. 5.11.1 L2 SRAM Initialization
    12. 5.12 ECC / Parity Protection for Accesses to Peripheral RAMs
    13. 5.13 On-Chip SRAM Initialization and Testing
      1. 5.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 5.13.1.1 Features
        2. 5.13.1.2 PBIST RAM Groups
      2. 5.13.2 On-Chip SRAM Auto Initialization
    14. 5.14 External Memory Interface (EMIF)
      1. 5.14.1 Features
      2. 5.14.2 Electrical and Timing Specifications
        1. 5.14.2.1 Read Timing (Asynchronous RAM)
        2. 5.14.2.2 Write Timing (Asynchronous RAM)
        3. 5.14.2.3 EMIF Asynchronous Memory Timing
        4. 5.14.2.4 Read Timing (Synchronous RAM)
        5. 5.14.2.5 Write Timing (Synchronous RAM)
        6. 5.14.2.6 EMIF Synchronous Memory Timing
    15. 5.15 Vectored Interrupt Manager
      1. 5.15.1 VIM Features
      2. 5.15.2 Interrupt Generation
      3. 5.15.3 Interrupt Request Assignments
    16. 5.16 ECC Error Event Monitoring and Profiling
      1. 5.16.1 EPC Module Operation
        1. 5.16.1.1 Correctable Error Handling
        2. 5.16.1.2 Uncorrectable Error Handling
    17. 5.17 DMA Controller
      1. 5.17.1 DMA Features
      2. 5.17.2 DMA Transfer Port Assignment
      3. 5.17.3 Default DMA Request Map
      4. 5.17.4 Using a GIO terminal as a DMA Request Input
    18. 5.18 Real-Time Interrupt Module
      1. 5.18.1 Features
      2. 5.18.2 Block Diagrams
      3. 5.18.3 Clock Source Options
      4. 5.18.4 Network Time Synchronization Inputs
    19. 5.19 Error Signaling Module
      1. 5.19.1 ESM Features
      2. 5.19.2 ESM Channel Assignments
    20. 5.20 Reset / Abort / Error Sources
    21. 5.21 Digital Windowed Watchdog
    22. 5.22 Debug Subsystem
      1. 5.22.1  Block Diagram
      2. 5.22.2  Debug Components Memory Map
      3. 5.22.3  Embedded Cross Trigger
      4. 5.22.4  JTAG Identification Code
      5. 5.22.5  Debug ROM
      6. 5.22.6  JTAG Scan Interface Timings
      7. 5.22.7  Advanced JTAG Security Module
      8. 5.22.8  Embedded Trace Macrocell (ETM-R5)
        1. 5.22.8.1 ETM TRACECLKIN Selection
        2. 5.22.8.2 Timing Specifications
      9. 5.22.9  RAM Trace Port (RTP)
        1. 5.22.9.1 RTP Features
        2. 5.22.9.2 Timing Specifications
      10. 5.22.10 Data Modification Module (DMM)
        1. 5.22.10.1 DMM Features
        2. 5.22.10.2 Timing Specifications
      11. 5.22.11 Boundary Scan Chain
  6. 6 Peripheral Information and Electrical Specifications
    1. 6.1  Enhanced Translator PWM Modules (ePWM)
      1. 6.1.1 ePWM Clocking and Reset
      2. 6.1.2 Synchronization of ePWMx Time-Base Counters
      3. 6.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 6.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 6.1.5 ePWM Synchronization with External Devices
      6. 6.1.6 ePWM Trip Zones
        1. 6.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 6.1.6.2 Trip Zone TZ4n
        3. 6.1.6.3 Trip Zone TZ5n
        4. 6.1.6.4 Trip Zone TZ6n
      7. 6.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 6.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
    2. 6.2  Enhanced Capture Modules (eCAP)
      1. 6.2.1 Clock Enable Control for eCAPx Modules
      2. 6.2.2 PWM Output Capability of eCAPx
      3. 6.2.3 Input Connection to eCAPx Modules
      4. 6.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    3. 6.3  Enhanced Quadrature Encoder (eQEP)
      1. 6.3.1 Clock Enable Control for eQEPx Modules
      2. 6.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 6.3.3 Input Connection to eQEPx Modules
      4. 6.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 6.4  12-bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 6.4.1 MibADC Features
      2. 6.4.2 Event Trigger Options
        1. 6.4.2.1 MibADC1 Event Trigger Hookup
        2. 6.4.2.2 MibADC2 Event Trigger Hookup
        3. 6.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 6.4.3 ADC Electrical and Timing Specifications
      4. 6.4.4 Performance (Accuracy) Specifications
        1. 6.4.4.1 MibADC Nonlinearity Errors
        2. 6.4.4.2 MibADC Total Error
    5. 6.5  General-Purpose Input/Output
      1. 6.5.1 Features
    6. 6.6  Enhanced High-End Timer (N2HET)
      1. 6.6.1 Features
      2. 6.6.2 N2HET RAM Organization
      3. 6.6.3 Input Timing Specifications
      4. 6.6.4 N2HET1-N2HET2 Interconnections
      5. 6.6.5 N2HET Checking
        1. 6.6.5.1 Internal Monitoring
        2. 6.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 6.6.6 Disabling N2HET Outputs
      7. 6.6.7 High-End Timer Transfer Unit (HET-TU)
        1. 6.6.7.1 Features
        2. 6.6.7.2 Trigger Connections
    7. 6.7  FlexRay Interface
      1. 6.7.1 Features
      2. 6.7.2 Electrical and Timing Specifications
      3. 6.7.3 FlexRay Transfer Unit
    8. 6.8  Controller Area Network (DCAN)
      1. 6.8.1 Features
      2. 6.8.2 Electrical and Timing Specifications
    9. 6.9  Local Interconnect Network Interface (LIN)
      1. 6.9.1 LIN Features
    10. 6.10 Serial Communication Interface (SCI)
      1. 6.10.1 Features
    11. 6.11 Inter-Integrated Circuit (I2C)
      1. 6.11.1 Features
      2. 6.11.2 I2C I/O Timing Specifications
    12. 6.12 Multibuffered / Standard Serial Peripheral Interface
      1. 6.12.1 Features
      2. 6.12.2 MibSPI Transmit and Receive RAM Organization
      3. 6.12.3 MibSPI Transmit Trigger Events
        1. 6.12.3.1 MIBSPI1 Event Trigger Hookup
        2. 6.12.3.2 MIBSPI2 Event Trigger Hookup
        3. 6.12.3.3 MIBSPI3 Event Trigger Hookup
        4. 6.12.3.4 MIBSPI4 Event Trigger Hookup
        5. 6.12.3.5 MIBSPI5 Event Trigger Hookup
      4. 6.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 6.12.5 SPI Slave Mode I/O Timings
    13. 6.13 Ethernet Media Access Controller
      1. 6.13.1 Ethernet MII Electrical and Timing Specifications
      2. 6.13.2 Ethernet RMII Electrical and Timing Specifications
      3. 6.13.3 Management Data Input/Output (MDIO)
  7. 7 Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Receiving Notification of Documentation Updates
      3. 8.2.3 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
        1. Table 8-1 Device ID Bit Allocation Register Field Descriptions
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 FlexRay Certifications
      2. 8.7.2 DCAN Certification
      3. 8.7.3 LIN Certification
        1. 8.7.3.1 LIN Master Mode
        2. 8.7.3.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.3.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9 Mechanical Data
    1. 9.1 Packaging Information
  10. 10Package Option Addendum
    1. 10.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6.2.1 Clock Domain Descriptions

Table 5-16 lists the device clock domains and their default clock sources. Table 5-16 also lists the system module control register that is used to select an available clock source for each clock domain.

Table 5-16 Clock Domain Descriptions

CLOCK DOMAIN CLOCK DISABLE BIT DEFAULT
SOURCE 		SOURCE SELECTION
REGISTER 		SPECIAL CONSIDERATIONS
GCLK1 SYS.CDDIS.0 OSCIN SYS.GHVSRC[3:0]
  • This the main clock from which HCLK is divided down
  • In phase with HCLK
  • Is disabled separately from HCLK through the CDDISx registers bit 0
  • Can be divided-by-1 up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
GCLK2 SYS.CDDIS.0 OSCIN SYS.GHVSRC[3:0]
  • Always the same frequency as GCLK1
  • 2 cycles delayed from GCLK1
  • Is disabled along with GCLK1
  • Gets divided by the same divider setting as that for GCLK1 when running CPU self-test (LBIST)
HCLK SYS.CDDIS.1 OSCIN SYS.GHVSRC[3:0]
  • Divided from GCLK1 through HCLKCNTLregister
  • Allowable clock ratio from 1:1 to 4:1
  • Is disabled through the CDDISx registers bit 1
VCLK SYS.CDDIS.2 OSCIN SYS.GHVSRC[3:0]
  • Divided down from HCLK through CLKCNTL register
  • Can be HCLK/1, HCLK/2,... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 2
  • HCLK:VCLK2:VCLK must be integer ratios of each other
VCLK2 SYS.CDDIS.3 OSCIN SYS.GHVSRC[3:0]
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2,... or HCLK/16
  • Frequency must be an integer multiple of VCLK frequency
  • Is disabled separately from HCLK through the CDDISx registers bit 3
VCLK3 SYS.CDDIS.8 OSCIN SYS.GHVSRC[3:0]
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2,... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 8
VCLKA1 SYS.CDDIS.4 VCLK SYS.VCLKASRC[3:0]
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 4
VCLKA2 SYS.CDDIS.5 VCLK SYS.VCLKASRC[3:0]
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 5
VCLKA4 SYS.CDDIS.11 VCLK SYS.VCLKACON1[19:16]
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 11
VCLKA4_DIVR SYS.VCLKACON1.20 VCLK SYS.VCLKACON1[19:16]
  • Divided down from VCLKA4 using the VCLKA4R field of the VCLKACON1 register
  • Frequency can be VCLKA4/1, VCLKA4/2, ..., or VCLKA4/8
  • Default frequency is VCLKA4/2
  • Is disabled separately through the VCLKA4_DIV_CDDIS bit in the VCLKACON1 register, if the VCLKA4 is not already disabled
RTICLK1 SYS.CDDIS.6 VCLK SYS.RCLKSRC[3:0]
  • Defaults to VCLK as the source
  • If a clock source other than VCLK is selected for RTICLK1, then the RTICLK1 frequency must be less than or equal to VCLK/3
  • Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
  • Is disabled through the CDDISx registers bit 6