JAJSTJ4A June   2022  – March 2024 TMS570LC4357-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 GWT BGA Package Ball-Map (337 Terminal Grid Array)
    2. 5.2 Terminal Functions
      1. 5.2.1 GWT Package
        1. 5.2.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 5.2.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 5.2.1.3  RAM Trace Port (RTP)
        4. 5.2.1.4  Enhanced Capture Modules (eCAP)
        5. 5.2.1.5  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        6. 5.2.1.6  Enhanced Pulse-Width Modulator Modules (ePWM)
        7. 5.2.1.7  Data Modification Module (DMM)
        8. 5.2.1.8  General-Purpose Input / Output (GIO)
        9. 5.2.1.9  FlexRay Interface Controller (FlexRay)
        10. 5.2.1.10 Controller Area Network Controllers (DCAN)
        11. 5.2.1.11 Local Interconnect Network Interface Module (LIN)
        12. 5.2.1.12 Standard Serial Communication Interface (SCI)
        13. 5.2.1.13 Inter-Integrated Circuit Interface Module (I2C)
        14. 5.2.1.14 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        15. 5.2.1.15 Ethernet Controller
        16. 5.2.1.16 External Memory Interface (EMIF)
        17. 5.2.1.17 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)
        18. 5.2.1.18 System Module Interface
        19. 5.2.1.19 Clock Inputs and Outputs
        20. 5.2.1.20 Test and Debug Modules Interface
        21. 5.2.1.21 Flash Supply and Test Pads
        22. 5.2.1.22 Supply for Core Logic: 1.2-V Nominal
        23. 5.2.1.23 Supply for I/O Cells: 3.3-V Nominal
        24. 5.2.1.24 Ground Reference for All Supplies Except VCCAD
        25. 5.2.1.25 Other Supplies
      2. 5.2.2 Multiplexing
        1. 5.2.2.1 Output Multiplexing
          1. 5.2.2.1.1 Notes on Output Multiplexing
        2. 5.2.2.2 Input Multiplexing
          1. 5.2.2.2.1 Notes on Input Multiplexing
          2. 5.2.2.2.2 General Rules for Multiplexing Control Registers
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 6.6  Wait States Required - L2 Memories
    7. 6.7  Power Consumption Summary
    8. 6.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 6.9  Thermal Resistance Characteristics for the BGA Package (GWT)
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Output Buffer Drive Strengths
      2. 6.10.2 Input Timings
      3. 6.10.3 Output Timings
  8. 7 System Information and Electrical Specifications
    1. 7.1  Device Power Domains
    2. 7.2  Voltage Monitor Characteristics
      1. 7.2.1 Important Considerations
      2. 7.2.2 Voltage Monitor Operation
      3. 7.2.3 Supply Filtering
    3. 7.3  Power Sequencing and Power-On Reset
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down Sequence
      3. 7.3.3 Power-On Reset: nPORRST
        1. 7.3.3.1 nPORRST Electrical and Timing Requirements
    4. 7.4  Warm Reset (nRST)
      1. 7.4.1 Causes of Warm Reset
      2. 7.4.2 nRST Timing Requirements
    5. 7.5  Arm Cortex-R5F CPU Information
      1. 7.5.1 Summary of Arm Cortex-R5F CPU Features
      2. 7.5.2 Dual Core Implementation
      3.      73
      4. 7.5.3 Duplicate Clock Tree After GCLK
      5. 7.5.4 Arm Cortex-R5F CPU Compare Module (CCM) for Safety
        1. 7.5.4.1 Signal Compare Operating Modes
          1. 7.5.4.1.1 Active Compare Lockstep Mode
          2. 7.5.4.1.2 Self-Test Mode
          3. 7.5.4.1.3 Error Forcing Mode
          4. 7.5.4.1.4 Self-Test Error Forcing Mode
        2. 7.5.4.2 Bus Inactivity Monitor
        3. 7.5.4.3 CPU Registers Initialization
      6. 7.5.5 CPU Self-Test
        1. 7.5.5.1 Application Sequence for CPU Self-Test
        2. 7.5.5.2 CPU Self-Test Clock Configuration
        3. 7.5.5.3 CPU Self-Test Coverage
      7. 7.5.6 N2HET STC / LBIST Self-Test Coverage
    6. 7.6  Clocks
      1. 7.6.1 Clock Sources
        1. 7.6.1.1 Main Oscillator
          1. 7.6.1.1.1 Timing Requirements for Main Oscillator
        2. 7.6.1.2 Low-Power Oscillator
          1. 7.6.1.2.1 Features
          2.        94
          3. 7.6.1.2.2 LPO Electrical and Timing Specifications
        3. 7.6.1.3 Phase-Locked Loop (PLL) Clock Modules
          1. 7.6.1.3.1 Block Diagram
          2. 7.6.1.3.2 PLL Timing Specifications
        4. 7.6.1.4 External Clock Inputs
      2. 7.6.2 Clock Domains
        1. 7.6.2.1 Clock Domain Descriptions
        2. 7.6.2.2 Mapping of Clock Domains to Device Modules
      3. 7.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      4. 7.6.4 Clock Test Mode
    7. 7.7  Clock Monitoring
      1. 7.7.1 Clock Monitor Timings
      2. 7.7.2 External Clock (ECLK) Output Functionality
      3. 7.7.3 Dual Clock Comparators
        1. 7.7.3.1 Features
        2. 7.7.3.2 Mapping of DCC Clock Source Inputs
    8. 7.8  Glitch Filters
    9. 7.9  Device Memory Map
      1. 7.9.1 Memory Map Diagram
      2. 7.9.2 Memory Map Table
      3. 7.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 7.9.4 Master/Slave Access Privileges
        1. 7.9.4.1 Special Notes on Accesses to Certain Slaves
      5. 7.9.5 MasterID to PCRx
      6. 7.9.6 CPU Interconnect Subsystem SDC MMR Port
      7. 7.9.7 Parameter Overlay Module (POM) Considerations
    10. 7.10 Flash Memory
      1. 7.10.1 Flash Memory Configuration
      2. 7.10.2 Main Features of Flash Module
      3. 7.10.3 ECC Protection for Flash Accesses
      4. 7.10.4 Flash Access Speeds
      5. 7.10.5 Flash Program and Erase Timings
        1. 7.10.5.1 Flash Program and Erase Timings for Program Flash
        2. 7.10.5.2 Flash Program and Erase Timings for Data Flash
    11. 7.11 L2RAMW (Level 2 RAM Interface Module)
      1. 7.11.1 L2 SRAM Initialization
    12. 7.12 ECC / Parity Protection for Accesses to Peripheral RAMs
    13. 7.13 On-Chip SRAM Initialization and Testing
      1. 7.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 7.13.1.1 Features
        2. 7.13.1.2 PBIST RAM Groups
      2. 7.13.2 On-Chip SRAM Auto Initialization
    14. 7.14 External Memory Interface (EMIF)
      1. 7.14.1 Features
      2. 7.14.2 Electrical and Timing Specifications
        1. 7.14.2.1 Read Timing (Asynchronous RAM)
        2. 7.14.2.2 Write Timing (Asynchronous RAM)
        3. 7.14.2.3 EMIF Asynchronous Memory Timing
        4. 7.14.2.4 Read Timing (Synchronous RAM)
        5. 7.14.2.5 Write Timing (Synchronous RAM)
        6. 7.14.2.6 EMIF Synchronous Memory Timing
    15. 7.15 Vectored Interrupt Manager
      1. 7.15.1 VIM Features
      2. 7.15.2 Interrupt Generation
      3. 7.15.3 Interrupt Request Assignments
    16. 7.16 ECC Error Event Monitoring and Profiling
      1. 7.16.1 EPC Module Operation
        1. 7.16.1.1 Correctable Error Handling
        2. 7.16.1.2 Uncorrectable Error Handling
    17. 7.17 DMA Controller
      1. 7.17.1 DMA Features
      2. 7.17.2 DMA Transfer Port Assignment
      3. 7.17.3 Default DMA Request Map
      4. 7.17.4 Using a GIO terminal as a DMA Request Input
    18. 7.18 Real-Time Interrupt Module
      1. 7.18.1 Features
      2. 7.18.2 Block Diagrams
      3. 7.18.3 Clock Source Options
      4. 7.18.4 Network Time Synchronization Inputs
    19. 7.19 Error Signaling Module
      1. 7.19.1 ESM Features
      2. 7.19.2 ESM Channel Assignments
    20. 7.20 Reset / Abort / Error Sources
    21. 7.21 Digital Windowed Watchdog
    22. 7.22 Debug Subsystem
      1. 7.22.1  Block Diagram
      2. 7.22.2  Debug Components Memory Map
      3. 7.22.3  Embedded Cross Trigger
      4. 7.22.4  JTAG Identification Code
      5. 7.22.5  Debug ROM
      6. 7.22.6  JTAG Scan Interface Timings
      7. 7.22.7  Advanced JTAG Security Module
      8. 7.22.8  Embedded Trace Macrocell (ETM-R5)
        1. 7.22.8.1 ETM TRACECLKIN Selection
        2. 7.22.8.2 Timing Specifications
      9. 7.22.9  RAM Trace Port (RTP)
        1. 7.22.9.1 RTP Features
        2. 7.22.9.2 Timing Specifications
      10. 7.22.10 Data Modification Module (DMM)
        1. 7.22.10.1 DMM Features
        2. 7.22.10.2 Timing Specifications
      11. 7.22.11 Boundary Scan Chain
  9. 8 Peripheral Information and Electrical Specifications
    1. 8.1  Enhanced Translator PWM Modules (ePWM)
      1. 8.1.1 ePWM Clocking and Reset
      2. 8.1.2 Synchronization of ePWMx Time-Base Counters
      3. 8.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 8.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 8.1.5 ePWM Synchronization with External Devices
      6. 8.1.6 ePWM Trip Zones
        1. 8.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 8.1.6.2 Trip Zone TZ4n
        3. 8.1.6.3 Trip Zone TZ5n
        4. 8.1.6.4 Trip Zone TZ6n
      7. 8.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 8.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
    2. 8.2  Enhanced Capture Modules (eCAP)
      1. 8.2.1 Clock Enable Control for eCAPx Modules
      2. 8.2.2 PWM Output Capability of eCAPx
      3. 8.2.3 Input Connection to eCAPx Modules
      4. 8.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    3. 8.3  Enhanced Quadrature Encoder (eQEP)
      1. 8.3.1 Clock Enable Control for eQEPx Modules
      2. 8.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 8.3.3 Input Connection to eQEPx Modules
      4. 8.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 8.4  12-bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 8.4.1 MibADC Features
      2. 8.4.2 Event Trigger Options
        1. 8.4.2.1 MibADC1 Event Trigger Hookup
        2. 8.4.2.2 MibADC2 Event Trigger Hookup
        3. 8.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 8.4.3 ADC Electrical and Timing Specifications
      4. 8.4.4 Performance (Accuracy) Specifications
        1. 8.4.4.1 MibADC Nonlinearity Errors
        2. 8.4.4.2 MibADC Total Error
    5. 8.5  General-Purpose Input/Output
      1. 8.5.1 Features
    6. 8.6  Enhanced High-End Timer (N2HET)
      1. 8.6.1 Features
      2. 8.6.2 N2HET RAM Organization
      3. 8.6.3 Input Timing Specifications
      4. 8.6.4 N2HET1-N2HET2 Interconnections
      5. 8.6.5 N2HET Checking
        1. 8.6.5.1 Internal Monitoring
        2. 8.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 8.6.6 Disabling N2HET Outputs
      7. 8.6.7 High-End Timer Transfer Unit (HET-TU)
        1. 8.6.7.1 Features
        2. 8.6.7.2 Trigger Connections
    7. 8.7  FlexRay Interface
      1. 8.7.1 Features
      2. 8.7.2 Electrical and Timing Specifications
      3. 8.7.3 FlexRay Transfer Unit
    8. 8.8  Controller Area Network (DCAN)
      1. 8.8.1 Features
      2. 8.8.2 241
      3. 8.8.3 Electrical and Timing Specifications
    9. 8.9  Local Interconnect Network Interface (LIN)
      1. 8.9.1 LIN Features
    10. 8.10 Serial Communication Interface (SCI)
      1. 8.10.1 Features
    11. 8.11 Inter-Integrated Circuit (I2C)
      1. 8.11.1 Features
      2. 8.11.2 I2C I/O Timing Specifications
    12. 8.12 Multibuffered / Standard Serial Peripheral Interface
      1. 8.12.1 Features
      2. 8.12.2 MibSPI Transmit and Receive RAM Organization
      3. 8.12.3 MibSPI Transmit Trigger Events
        1. 8.12.3.1 MIBSPI1 Event Trigger Hookup
        2. 8.12.3.2 MIBSPI2 Event Trigger Hookup
        3. 8.12.3.3 MIBSPI3 Event Trigger Hookup
        4. 8.12.3.4 MIBSPI4 Event Trigger Hookup
        5. 8.12.3.5 MIBSPI5 Event Trigger Hookup
      4. 8.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 8.12.5 SPI Slave Mode I/O Timings
    13. 8.13 Ethernet Media Access Controller
      1. 8.13.1 Ethernet MII Electrical and Timing Specifications
      2. 8.13.2 Ethernet RMII Electrical and Timing Specifications
      3. 8.13.3 Management Data Input/Output (MDIO)
  10. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device and Development-Support Tool Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation from Texas Instruments
      2. 10.2.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
    7. 10.7 Device Identification
      1. 10.7.1 Device Identification Code Register
      2. 10.7.2 Die Identification Registers
    8. 10.8 Module Certifications
      1. 10.8.1 FlexRay Certifications
      2. 10.8.2 DCAN Certification
      3. 10.8.3 LIN Certification
        1. 10.8.3.1 LIN Master Mode
        2. 10.8.3.2 LIN Slave Mode - Fixed Baud Rate
        3. 10.8.3.3 LIN Slave Mode - Adaptive Baud Rate
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

7.22.3 Embedded Cross Trigger

The Embedded Cross Trigger (ECT) is a modular component that supports the interaction and synchronization of multiple triggering events within a SoC.

The ECT consists of two modules:

  • A (Cross Trigger Interface) CTI. The CTI provides the interface between a component or subsystem and the Cross Trigger Matrix (CTM).
  • A CTM. The CTM combines the trigger requests generated from CTIs and broadcasts them to all CTIs as channel triggers. This enables subsystems to interact, cross trigger, with one another.
GUID-63443466-C011-48BC-8925-A71833C7BA3F-low.gifFigure 7-24 CTI/CTM Integration
GUID-D4156336-0D36-4FDC-BB95-1DDAB5F5C9A8-low.gifFigure 7-25 CTI1 Mapping
Note:

ETM-R5, Cortex-R5F and CTI1 run at same frequency.

Table 7-48 CTI1 Mapping
CTI TRIGGERModule Signal
Trigger Input 0From Cortex-R5F DBTRIGGER
Trigger Input 1From Cortex-R5F nPMUIRQ
Trigger Input 2From ETM-R5 EXTOUT[0]
Trigger Input 3From ETM-R5 EXTOUT[1]
Trigger Input 4From Cortex-R5F COMMRX
Trigger Input 5From Cortex-R5F COMMTX
Trigger Input 6From ETM-R5 TRIGGER
Trigger Input 7From Cortex-R5F DBTRIGGER
Trigger Output 0To Cortex-R5F EDBGRQ
Trigger Output 1To ETM-R5 EXTIN[0]
Trigger Output 2To ETM-R5 EXTIN[1]
Trigger Output 3To Cortex-R5F nIRQ
Trigger Output 4Reserved
Trigger Output 5Reserved
Trigger Output 6Reserved
Trigger Output 7To Cortex-R5F DBGRESTARTED
GUID-B2B37AFE-5274-4A9C-BBA2-3D17CAE18B6B-low.gifFigure 7-26 CTI3 Mapping
Note:

TPIU and CTI3 run at different frequencies.

Table 7-49 CTI3 Mapping
CTI TRIGGERModule Signal
Trigger Input 0Reserved
Trigger Input 1Reserved
Trigger Input 2Reserved
Trigger Input 3Reserved
Trigger Input 4Reserved
Trigger Input 5Reserved
Trigger Input 6Reserved
Trigger Input 7Reserved
Trigger Output 0To TPIU TRIGIN
Trigger Output 1To TPIU FLUSHIN
Trigger Output 2Reserved
Trigger Output 3Reserved
Trigger Output 4Reserved
Trigger Output 5Reserved
Trigger Output 6Reserved
Trigger Output 7Reserved
GUID-5814B709-CD64-45BD-807E-C73F6D0EA0C3-low.gifFigure 7-27 CTI4 Mapping
Table 7-50 CTI4 Mapping
CTI TRIGGERModule Signal
Trigger Input 0From DMA_DBGREQ
Trigger Input 1From N2HET1_DBGREQ
Trigger Input 2From N2HET2_DBGREQ
Trigger Input 3From HTU1_DBGREQ
Trigger Input 4From HTU2_DBGREQ
Trigger Input 5From DMA_DBGREQ
Trigger Input 6From N2HET1_DBGREQ or HTU1_DBGREQ
Trigger Input 7From N2HET2_DBGREQ or HTU2_DBGREQ
Trigger Output 0To SYS_MODULE_TRIGGER
Trigger Output 1To USER_PERIPHERAL_TRIGGER1
Trigger Output 2To USER_PERIPHERAL_TRIGGER2
Trigger Output 3To USER_PERIPHERAL_TRIGGER3
Trigger Output 4To IcePick Debug_Attention
Trigger Output 5Reserved
Trigger Output 6Reserved
Trigger Output 7Reserved
Table 7-51 Peripheral Suspend Generation
TRIGGER OUTPUTMODULE SIGNAL CONNECTEDDESCRIPTION
SYS_MODULE_TRIGGERL2FMC_CPU_EMUSUSPL2FMC Wrapper Suspend
CCM_R5_CPU_EMUSUSPCCM_R5 module suspend
CRC_CPU_EMUSUSPCRC1 / CRC2 module suspend
SYS_CPU_EMUSUSPSYS module Suspend
USER_PERIPHERAL_TRIGGER1DMA_SUSPENDDMA Suspend
RTI_CPU_SUSPENDRTI1 / RTI2 Suspend
AWM_CPU_SUSPENDAWM1 / AWM2 Suspend
HTU_CPU_EMUSUSPHTU1 / HTU2 Suspend
SCI_CPU_EMUSUSPSCI3 / SCI4 Suspend
LIN_CPU_EMUSUSPLIN1 / LIN2 Suspend
I2C_CPU_EMUSUSPI2C1 / I2C2 Suspend
EMAC_CPU_EMUSUSPEMAC Suspend
EQEP_CPU_EMUSUSPEQEP Suspend
ECAP_CPU_EMUSUSPECAP Suspend
DMM_CPU_EMUSUSPDMM Suspend
 DCC_CPU_EMUSUSPDCC1 / DCC2 Suspend
USER_PERIPHERAL_TRIGGER2DCAN_CPU_EMUSUSPDCAN1 / DCAN2 / DCAN3 / DCAN4 Suspend
USER_PERIPHERAL_TRIGGER3ePWM_CPU_EMUSUSPePWM1..7 Trip Zone TZ6n and ePWM1..7 Suspend