6.2.1 Important Considerations

• The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
• The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The I/O supply must be above the threshold for monitoring the core supply. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter.

6.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

Table 6-2 lists the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

6.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (for more details, see Table 6-3), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000.

6.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.3.3.1 nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO.			MIN	MAX	UNIT
	VCCPORL	VCC low supply level when nPORRST must be active during power up		0.5	V
	VCCPORH	VCC high supply level when nPORRST must remain active during power up and become active during power down	1.14		V
	VCCIOPORL	VCCIO / VCCP low supply level when nPORRST must be active during power up		1.1	V
	VCCIOPORH	VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down	3.0		V
	VIL(PORRST)	Low-level input voltage of nPORRST VCCIO > 2.5 V		0.2 * VCCIO	V
		Low-level input voltage of nPORRST VCCIO < 2.5 V		0.5
3	tsu(PORRST)	Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up	0		ms
6	th(PORRST)	Hold time, nPORRST active after VCC > VCCPORH	1		ms
7	tsu(PORRST)	Setup time, nPORRST active before VCC < VCCPORH during power down	2		µs
8	th(PORRST)	Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH	1		ms
9	th(PORRST)	Hold time, nPORRST active after VCC < VCCPORL	0		ms
	tf(nPORRST)	Filter time nPORRST terminal; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset. Pulses greater than MIN but less than MAX may or may not generate a reset.	475	2000	ns

A. Figure 6-1 shows that there is no timing dependency between the ramp of the V_CCIO and the V_CC supply voltages.

Figure 6-1 nPORRST Timing Diagram^(A)

6.4.1 Causes of Warm Reset

6.4.2 nRST Timing Requirements

6.5.1 Summary of ARM Cortex-R5F CPU Features

The features of the ARM Cortex-R5F CPU include:

• An integer unit with integral Embedded ICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
• Floating-Point Coprocessor
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Nonmaskable interrupt.
• Harvard Level one (L1) memory system with:
  • 32KB of instruction cache and 32KB of data cache implemented. Both Instruction and data cache have ECC support.
  • ARMv7-R architecture Memory Protection Unit (MPU) with 16 regions
• Dual core logic for fault detection in safety-critical applications.
• L2 memory interface:
  • Single 64-bit master AXI interface
  • 64-bit slave AXI interface to cache memories
  • 32-bit AXI_Peri ports to support low latency peripheral ports
• Debug interface to a CoreSight Debug Access Port (DAP).
• Performance Monitoring Unit (PMU).
• Vectored Interrupt Controller (VIC) port.
• AXI accelerator coherency port (ACP) supporting IO coherency with write-through cacheable regions
• Ability to generate ECC on L2 data buses and parity of all control channels
• Both CPU cores in lock-step
• Eight hardware breakpoints
• Eight watchpoints

6.5.2 Dual Core Implementation

The device has two Cortex-R5F cores, where the output signals of both CPUs are compared in the CCM-R5F unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two clock cycles as shown in Figure 6-2.

6.5.3 Duplicate Clock Tree After GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-2.

6.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety

CCM-R5F has two major functions. One is to compare the outputs of two Cortex-R5F processor cores and the VIM modules. The second function is inactivity monitoring, to detect any faulted transaction initiated by the checker core.

6.5.4.3 CPU Registers Initialization

To avoid an erroneous CCM-R5F compare error, the application software must ensure that the CPU registers of both CPUs are initialized with the same values before the registers are used, including function calls where the register values are pushed onto the stack.

Example routine for CPU register initialization:

6.5.5 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R5F CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test as well as running few intervals at a time
• Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set)
• Complete isolation of the self-tested CPU core from rest of the system during the self-test run
• Ability to capture the Failure interval number
• Time-out counter for the CPU self-test run as a fail-safe feature

6.5.6 N2HET STC / LBIST Self-Test Coverage

Logic BIST self-test capability for N2HETs is available in this device. The STC2 can be configured to perform self-test for both N2HETs at the same time or one at the time. The default value of the N2HET LBIST clock prescaler is divide-by-1. However, the maximum clock rate for the N2HET STC / LBIST is VCLK/2. N2HET STC test should not be executed concurrently with CPU STC test.

6.6.1 Clock Sources

Table 6-11 lists the available clock sources on the device. Each clock source can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

Table 6-11 also lists the default state of each clock source.

6.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-3. The oscillator is a single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

NOTE

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine which load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature and voltage extremes.

An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN terminal and leaving the OSCOUT terminal unconnected (open) as shown in Figure 6-3.

Figure 6-3 Recommended Crystal/Clock Connection

6.6.1.1.1 Timing Requirements for Main Oscillator

Table 6-12 Timing Requirements for Main Oscillator

		MIN	NOM	MAX	UNIT
tc(OSC)	Cycle time, OSCIN (when using a sine-wave input)	50		200	ns
tc(OSC_SQR)	Cycle time, OSCIN, (when input to the OSCIN is a square wave)	50		200	ns
tw(OSCIL)	Pulse duration, OSCIN low (when input to the OSCIN is a square wave)	15			ns
tw(OSCIH)	Pulse duration, OSCIN high (when input to the OSCIN is a square wave)	15			ns

6.6.1.2 Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

6.6.1.2.1 Features

The main features of the LPO are:

• Supplies a clock at extremely low power to reduce power consumption. This is connected as clock source 4 of the Global Clock Module (GCM).
• Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source 5 of the GCM.
• Provides a comparison clock for the crystal oscillator failure detection circuit.

Figure 6-4 LPO Block Diagram

Figure 6-4 shows a block diagram of the internal reference oscillator. This is a low-power oscillator (LPO) and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

6.6.1.2.2 LPO Electrical and Timing Specifications

Table 6-13 LPO Specifications

PARAMETER		MIN	TYP	MAX	UNIT
Clock detection	Oscillator fail frequency - lower threshold, using untrimmed LPO output	1.375	2.4	4.875	MHz
	Oscillator fail frequency - higher threshold, using untrimmed LPO output	22	38.4	78	MHz
LPO - HF oscillator	Untrimmed frequency	5.5	9	19.5	MHz
	Trimmed frequency	8.0	9.6	11.0	MHz
	Start-up time from STANDBY (LPO BIAS_EN high for at least 900 µs)			10	µs
	Cold start-up time			900	µs
LPO - LF oscillator	Untrimmed frequency	36	85	180	kHz
	Start-up time from STANDBY (LPO BIAS_EN high for at least 900 µs)			100	µs
	Cold start-up time			2000	µs

6.6.1.3 Phase-Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled.
• Configurable frequency multipliers and dividers
• Built-in PLL Slip monitoring circuit
• Option to reset the device on a PLL slip detection

6.6.1.3.1 Block Diagram

Figure 6-5 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2.

Figure 6-5 ZWT PLLx Block Diagram

6.6.1.3.2 PLL Timing Specifications

Table 6-14 PLL Timing Specifications

PARAMETER		MIN	MAX	UNIT
fINTCLK	PLL1 Reference Clock frequency	1	20	MHz
fpost_ODCLK	Post-ODCLK – PLL1 Post-divider input clock frequency		400	MHz
fVCOCLK	VCOCLK – PLL1 Output Divider (OD) input clock frequency		550	MHz
fINTCLK2	PLL2 Reference Clock frequency	1	20	MHz
fpost_ODCLK2	Post-ODCLK – PLL2 Post-divider input clock frequency		400	MHz
fVCOCLK2	VCOCLK – PLL2 Output Divider (OD) input clock frequency		550	MHz

6.6.2 Clock Domains

6.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in Figure 6-6.

Figure 6-6 Device Clock Domains

6.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC

Some applications may need to use both the FlexRay and the Ethernet interfaces. The FlexRay controller requires the VCLKA2 frequency to be 80 MHz, while the MII interface requires VCLKA4_DIVR_EMAC to be 25 MHz and the RMII requires VCLKA4_DIVR_EAMC to be 50 MHz.

These different frequencies are supported by adding special dedicated clock source selection options for the VCLKA4_DIVR_EMAC clock domain. This logic is shown in Figure 6-7.

Figure 6-7 VCLKA4_DIVR Source Selection Options

The PLL2 post_ODCLK is brought out as a separate output from the PLL wrapper module. There are two additional dividers implemented at the device-level to divide this PLL2 post_ODCLK by 8 and by 16.

As shown in Figure 6-7, the VCLKA4_SRC configured through the system module VCLKACON1 control register is used to determine the clock source for the VCLKA4 and VCLKA4_DIVR. An additional multiplexor is implemented to select between the VCLKA4_DIVR and the two additional clock sources – PLL2 post_ODCLK/8 and post_ODCLK/16.

Table 6-17 lists the VCLKA4_DIVR_EMAC clock source selections.

6.6.4 Clock Test Mode

The TMS570 platform architecture defines a special mode that allows various clock signals to be selected and output on the ECLK1 terminal and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. See Table 6-18 and Table 6-19 for the CLKTEST bits value and signal selection.

6.7.1 Clock Monitor Timings

Figure 6-8 LPO and Clock Detection, Untrimmed CLK10M

6.7.2 External Clock (ECLK) Output Functionality

The ECLK1/ECLK2 terminal can be configured to output a prescaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

6.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source. For example, the reference clock is connected to Counter 0 and the signal to be measured is connected to Counter 1. Counter 0 is programmed with a start value of known time duration (measurement time) from the reference clock. Counter 1 is programmed with a maximum start value. Start both counter simultaneously. When Counter 0 decrements to zero, both counter will stop and an error signal is generated if Counter 1 does not reach zero. The frequency of the input signals can be calculated from the count value of Counter 1 and the measurement time.

Table 6-24 Glitch Filter Timing Specifications

6.9.1 Memory Map Diagram

Figure 6-9 shows the device memory map.

6.9.2 Memory Map Table

6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program status register (CPSR).

6.9.4 Master/Slave Access Privileges

Table 6-26 and Table 6-27 list the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on either the CPU Interconnect Subsystem or the Peripheral Interconnect Subsystem is listed in Table 6-27. Allowed indicates that the module listed in the MASTERS column can access that slave module.

6.9.5 MasterID to PCRx

The MasterID associated with each master port on the Peripheral Interconnect Subsystem contains a 4-bit value. The MasterID is passed along with the address and control signals to three PCR modules. PCR decodes the address and control signals to select the peripheral. In addition, it decodes this 4-bit MasterID value to perform memory protection. With 4-bit of MasterID, it allows the PCR to distinguish among 16 different masters to allow or disallow access to a given peripheral. Associated with each peripheral a 16-bit MasterID access protection register is defined. Each bit grants or denies the permission of the corresponding binary coded decimal MasterID. For example, if bit 5 of the access permission register is set, it grants MasterID 5 to access the peripheral. If bit 7 is clear, it denies MasterID 7 to access the peripheral. Figure 6-10 shows the MasterID filtering scheme. Table 6-27 lists the MasterID of each master, which can access the PCRx.

Figure 6-10 PCR MasterID Filtering

6.9.6 CPU Interconnect Subsystem SDC MMR Port

The CPU Interconnect Subsystem SDC MMR Port is a special slave to the Peripheral Interconnect Subsystem. It is memory mapped at starting address of 0xFA00_0000. Various status registers pertaining to the diagnostics of the CPU Interconnect Subsystem can be access through this slave port. The CPU Interconnect Subsystem contains built-in hardware diagnostic checkers which will constantly watch transactions flowing through the interconnect. There is a checker for each master and slave attached to the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated behavior by the interconnect. For example, if the CPU issues a burst read request to the flash, the checker will ensure that the expected behavior is indeed a burst read request to the proper slave module. If the interconnects generates a transaction which is not a read, or not a burst or not to the flash as the destination, then the checker will flag it one of the registers. The detected error will also be signaled to the ESM module. Refer to the Interconnect chapter of the TRM SPNU563 for details on the registers.

6.9.7 Parameter Overlay Module (POM) Considerations

The Parameter Overlay Module (POM) is implemented as part of the L2FMC module. It is used to redirect flash memory accesses to external memory interfaces or internal SRAM. The POM has an OCP master port to redirect accesses. The POM MMRs are located in a separate block and read/writes will happen through the Debug APB port on the L2FMC. The POM master port is capable of read accesses only. Inside the CPU Subsystem SCR, the POM master port is connected to both the L2RAMW and EMIF slaves. The primary roles of the POM are:

• The POM snoops the access on the two flash slave ports to determine if access should be remapped or not. It supports 32 regions among the two slave ports.
• If access is to be remapped, then the POM kills the access to the flash bank, and instead redirects the access through its own master.
• Upon obtaining response, the POM populates the response FIFO of the respective port so that the response is delivered back to the original requester.
• The access is unaffected if the request is not mapped to any region, or if the POM is disabled.
• The POM does not add any latency to the flash access when it is turned off.
• The POM does not add any latency to the remapped access (except the latency, if any, associated with the getting the response from the an alternate slave)

6.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

6.10.2 Main Features of Flash Module

• Support for multiple flash banks for program and/or data storage
• Simultaneous read accesses on two banks while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Software interface for flash program and erase operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R5F CPU
• Support for a rich set of diagnostic features

6.10.3 ECC Protection for Flash Accesses

All accesses to the L2 program flash memory are protected by SECDED logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits data received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the 'X' bit of the Performance Monitor Control Register, c9.

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.

6.10.5 Flash Program and Erase Timings

6.11.1 L2 SRAM Initialization

The entire L2 SRAM can be globally initialized by setting the corresponding bit in SYS.MSINENA register. When initialized, the memory arrays are written with all zeros for the 64-bit data and the corresponding 8-bit ECC checksum. Hardware memory initialization eliminates ECC error when the CPU reads from an un-initialized memory location which can cause an ECC error. For more information, see the device-specific Technical Reference Manual.

6.13.1 On-Chip SRAM Self-Test Using PBIST

6.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the system module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers, see the device-specific Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is provided in Table 6-34.

6.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices. The EMIF features includes support for:

• 3 addressable chip select for asynchronous memories of up to 16MB each
• 1 addressable chip select space for SDRAMs up to 128MB
• 8 or 16-bit data bus width
• Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
• Select strobe mode
• Extended Wait mode
• Data bus parking

6.14.2 Electrical and Timing Specifications

6.14.2.1 Read Timing (Asynchronous RAM)

Figure 6-11 Asynchronous Memory Read Timing

Figure 6-12 EMIFnWAIT Read Timing Requirements

6.14.2.2 Write Timing (Asynchronous RAM)

Figure 6-13 Asynchronous Memory Write Timing

Figure 6-14 EMIFnWAIT Write Timing Requirements

6.14.2.4 Read Timing (Synchronous RAM)

Figure 6-15 Basic SDRAM Read Operation

6.14.2.5 Write Timing (Synchronous RAM)

Figure 6-16 Basic SDRAM Write Operation

6.15.1 VIM Features

The VIM module has the following features:

• Supports 128 interrupt channels
• Provides programmable priority for the request lines
• Manages interrupt channels through masking
• Prioritizes interrupt channels to the CPU
• Provides the CPU with the address of the interrupt service routine (ISR) for each interrupt

The two VIM modules are in lockstep. These two VIM modules are memory mapped to the same address space. From a programmer’s model point of view it is only one VIM module. Writes to VIM1 registers and memory will be broadcasted to both VIM1 and VIM2. Reads from VIM1 will only read the VIM1 registers and memory. All interrupt requests which go to the VIM1 module will also go to the VIM2 module. Because the VIM1 and VIM2 have the identical setup, both will result in the same output behavior responding to the same interrupt requests. The second VIM module acts as a diagnostic checker module against the first VIM module. The output signals of the two VIM modules are routed to CCM-R5F module and are compared constantly. Mis-compare detected will be signaled as an error to the ESM module. The lockstep VIM pair takes care of the interrupt generation to the lockstep R5F pair.

6.15.2 Interrupt Generation

To avoid common mode failures the input and output signals of the two VIMs are delayed in a different way as shown in Figure 6-17.

Figure 6-17 Interrupt Generation

6.15.3 Interrupt Request Assignments

6.16.1 EPC Module Operation

6.17.1 DMA Features

• 64-bit OCP protocol to perform bus master accesses
• INCR-4 64-bit burst accesses
• Multithreading architecture allowing data of two different channel transfers to be interleaved during nonburst accesses
• 2-port configuration for parallel bus master
• Channels can be assigned to either high-priority queue or low-priority queue. Within each queue, fixed or round-robin priorities can be serviced
• Built-in ECC generation and evaluation logic for internal RAM storing channel transfer information
• Supports multiple interrupt outputs for mapping to multiple interrupt controllers in multicore systems
• 48 requests can be mapped to any 32 channels
• Supports LE endianess
• External ECC Gen/Eval block of DMA support ECC generation for data transactions, and parity for address, and control signals (following Cortex-R5F standard)
• 8 MPU regions
• Channel chaining capability
• Hardware and software DMA requests
• 8-, 16-, 32-, or 64-bit transactions supported
• Multiple addressing modes for source/destination (fixed, increment, offset)
• Auto-initiation

6.17.2 DMA Transfer Port Assignment

There are two ports, port A and port B attached to the DMA controller. When configuring a DMA channel for a transfer, the application must also specify the port associated with the transfer source and destination. Table 6-40 lists the mapping between each port and the resources. For example, if a transfer is to be made from the the flash to the SRAM, the application will need configure the desired DMA channel in the PARx register to select port A as the target for both the source and destination. If a transfer is to be made from the SRAM to a peripheral or a peripheral memory, the application will need to configure the desired DMA channel in the PARx register to select port A for read and port B for write. Likewise, if a transfer is from a peripheral to the SRAM then the PARx will be configured to select port B for read and port A for write.

6.17.3 Default DMA Request Map

The DMA module on this microcontroller has 32 channels and up to 48 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, see Table 6-41. The application must ensure that only one of these DMA request sources is enabled at any time.

6.17.4 Using a GIO terminal as a DMA Request Input

Each GIO terminal can also directly be used as DMA request input as listed in Table 6-41. The polarity of the GIO terminal to trigger a DMA request can be selected inside the DMA module. To use the GIO terminal as a DMA request input, the corresponding select bit must be set to low. See Figure 6-19 for an illustration. For more information see the technical reference guide SPNU563.

Figure 6-19 Using a GIO terminal as a DMA Request Input

6.18.1 Features

The RTI module has the following features:

• Two independent 64-bit counter blocks
• Four configurable compares for generating operating system ticks or DMA requests. Each event can be driven by either counter block 0 or counter block 1.
• Fast enabling/disabling of events
• Two timestamp (capture) functions for system or peripheral interrupts, one for each counter block

6.18.2 Block Diagrams

Figure 6-20 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as time-base inputs for the counter block 0. Figure 6-21 shows the compare unit block diagram of the RTI module.

Figure 6-20 Counter Block Diagram

Figure 6-21 Compare Block Diagram

6.18.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the system module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources, see Table 6-11 and Table 6-16.

6.18.4 Network Time Synchronization Inputs

The RTI module supports four Network Time Unit (NTU) inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as shown in Table 6-43.

6.19.1 ESM Features

The features of the ESM are:

• 160 interrupt/error channels are supported, divided into three groups
  • 96 channels with maskable interrupt and configurable error terminal behavior
  • 32 error channels with nonmaskable interrupt and predefined error terminal behavior
  • 32 channels with predefined error terminal behavior only
• Error terminal to signal severe device failure
• Configurable time base for error signal
• Error forcing capability

6.19.2 ESM Channel Assignments

The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group to which the error is connected. Table 6-45 lists the channel assignment for each group.

Table 6-46 Reset/Abort/Error Sources