JAJSFJ6C October   2012  – May 2018 TMS570LS0332 , TMS570LS0432

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Terminal Functions
      1. 4.2.1  High-End Timer (N2HET)
      2. 4.2.2  Enhanced Quadrature Encoder Pulse Modules (eQEP)
      3. 4.2.3  General-Purpose Input/Output (GPIO)
      4. 4.2.4  Controller Area Network Interface Modules (DCAN1, DCAN2)
      5. 4.2.5  Multibuffered Serial Peripheral Interface (MibSPI1)
      6. 4.2.6  Standard Serial Peripheral Interface (SPI2)
      7. 4.2.7  Local Interconnect Network Controller (LIN)
      8. 4.2.8  Multibuffered Analog-to-Digital Converter (MibADC)
      9. 4.2.9  System Module
      10. 4.2.10 Error Signaling Module (ESM)
      11. 4.2.11 Main Oscillator
      12. 4.2.12 Test/Debug Interface
      13. 4.2.13 Flash
      14. 4.2.14 Core Supply
      15. 4.2.15 I/O Supply
      16. 4.2.16 Core and I/O Supply Ground Reference
    3. 4.3 Output Multiplexing and Control
      1. 4.3.1 Notes on Output Multiplexing
      2. 4.3.2 General Rules for Multiplexing Control Registers
    4. 4.4 Special Multiplexed Options
      1. 4.4.1 Filtering for eQEP Inputs
        1. 4.4.1.1 eQEPA Input
        2. 4.4.1.2 eQEPB Input
        3. 4.4.1.3 eQEPI Input
        4. 4.4.1.4 eQEPS Input
      2. 4.4.2 N2HET PIN_nDISABLE Input Port
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Thermal Resistance Characteristics for PZ
    9. 5.9  Input/Output Electrical Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
  6. 6System Information and Electrical Specifications
    1. 6.1  Voltage Monitor Characteristics
      1. 6.1.1 Important Considerations
      2. 6.1.2 Voltage Monitor Operation
      3. 6.1.3 Supply Filtering
    2. 6.2  Power Sequencing and Power-On Reset
      1. 6.2.1 Power-Up Sequence
      2. 6.2.2 Power-Down Sequence
      3. 6.2.3 Power-On Reset: nPORRST
        1. 6.2.3.1 nPORRST Electrical and Timing Requirements
    3. 6.3  Warm Reset (nRST)
      1. 6.3.1 Causes of Warm Reset
      2. 6.3.2 nRST Timing Requirements
    4. 6.4  ARM Cortex-R4 CPU Information
      1. 6.4.1 Summary of ARM Cortex-R4 CPU Features
      2. 6.4.2 ARM Cortex-R4 CPU Features Enabled by Software
      3. 6.4.3 Dual Core Implementation
      4. 6.4.4 Duplicate clock tree after GCLK
      5. 6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety
      6. 6.4.6 CPU Self-Test
        1. 6.4.6.1 Application Sequence for CPU Self-Test
        2. 6.4.6.2 CPU Self-Test Clock Configuration
        3. 6.4.6.3 CPU Self-Test Coverage
    5. 6.5  Clocks
      1. 6.5.1 Clock Sources
        1. 6.5.1.1 Main Oscillator
          1. 6.5.1.1.1 Timing Requirements for Main Oscillator
        2. 6.5.1.2 Low-Power Oscillator
          1. 6.5.1.2.1 Features
          2. 6.5.1.2.2 LPO Electrical and Timing Specifications
        3. 6.5.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.5.1.3.1 Block Diagram
          2. 6.5.1.3.2 PLL Timing Specifications
      2. 6.5.2 Clock Domains
        1. 6.5.2.1 Clock Domain Descriptions
        2. 6.5.2.2 Mapping of Clock Domains to Device Modules
      3. 6.5.3 Clock Test Mode
    6. 6.6  Clock Monitoring
      1. 6.6.1 Clock Monitor Timings
      2. 6.6.2 External Clock (ECLK) Output Functionality
      3. 6.6.3 Dual Clock Comparator
        1. 6.6.3.1 Features
        2. 6.6.3.2 Mapping of DCC Clock Source Inputs
    7. 6.7  Glitch Filters
    8. 6.8  Device Memory Map
      1. 6.8.1 Memory Map Diagram
      2. 6.8.2 Memory Map Table
      3. 6.8.3 Master/Slave Access Privileges
    9. 6.9  Flash Memory
      1. 6.9.1 Flash Memory Configuration
      2. 6.9.2 Main Features of Flash Module
      3. 6.9.3 ECC Protection for Flash Accesses
      4. 6.9.4 Flash Access Speeds
    10. 6.10 Flash Program and Erase Timings for Program Flash
    11. 6.11 Flash Program and Erase Timings for Data Flash
    12. 6.12 Tightly Coupled RAM Interface Module
      1. 6.12.1 Features
      2. 6.12.2 TCRAMW ECC Support
    13. 6.13 Parity Protection for Accesses to peripheral RAMs
    14. 6.14 On-Chip SRAM Initialization and Testing
      1. 6.14.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.14.1.1 Features
        2. 6.14.1.2 PBIST RAM Groups
      2. 6.14.2 On-Chip SRAM Auto Initialization
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
    17. 6.17 Error Signaling Module
      1. 6.17.1 Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset / Abort / Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 MIBADC Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4 Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET Checking
        1. 7.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)
      5. 7.4.5 Disabling N2HET Outputs
      6. 7.4.6 High-End Timer Transfer Unit (N2HET)
        1. 7.4.6.1 Features
        2. 7.4.6.2 Trigger Connections
    5. 7.5 Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6 Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7 Multibuffered / Standard Serial Peripheral Interface
      1. 7.7.1 Features
      2. 7.7.2 MibSPI Transmit and Receive RAM Organization
      3. 7.7.3 MibSPI Transmit Trigger Events
        1. 7.7.3.1 MIBSPI1 Event Trigger Hookup
      4. 7.7.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.7.5 SPI Slave Mode I/O Timings
    8. 7.8 Enhanced Quadrature Encoder (eQEP)
      1. 7.8.1 Clock Enable Control for eQEPx Modules
      2. 7.8.2 Using eQEPx Phase Error
      3. 7.8.3 Input Connections to eQEPx Modules
      4. 7.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  デバイス・サポート
      1. 8.1.1 開発サポート
        1. 8.1.1.1 はじめに
      2. 8.1.2 デバイスの項目表記
    2. 8.2  ドキュメントのサポート
      1. 8.2.1 テキサス・インスツルメンツの関連資料
    3. 8.3  関連リンク
    4. 8.4  Community Resources
    5. 8.5  商標
    6. 8.6  静電気放電に関する注意事項
    7. 8.7  Glossary
    8. 8.8  デバイス識別コード・レジスタ
      1. Table 8-2 デバイスIDビット割り当てレジスタのフィールドの説明
    9. 8.9  ダイ識別レジスタ
    10. 8.10 モジュール認定
      1. 8.10.1 DCAN認定
      2. 8.10.2 LIN認定
        1. 8.10.2.1 LINマスタ・モード
        2. 8.10.2.2 LINスレーブ・モード - 固定ボーレート
        3. 8.10.2.3 LINスレーブ・モード - 適応型ボーレート
  9. 9メカニカル、パッケージ、および注文に関する付録
    1. 9.1 パッケージ情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.5 SPI Slave Mode I/O Timings

Table 7-15 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 20 ns
td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 4 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 4
7(6) th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 2 ns
th(SPCH-SIMO)S Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) 2
8 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 22 ns
td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) + 22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+27 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-6.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
TMS570LS0432 TMS570LS0332 slave_mode_external_timing_phase0_pns160.gifFigure 7-10 SPI Slave Mode External Timing (CLOCK PHASE = 0)
TMS570LS0432 TMS570LS0332 slave_mode_enable_timing_phase0_pns160.gifFigure 7-11 SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

Table 7-16 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SOMI-SPCL)S Dealy time, SPISOMI data valid after SPICLK low (clock polarity = 0) trf(SOMI) + 20 ns
td(SOMI-SPCH)S Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4
7(6) tv(SPCH-SIMO)S High time, SPISIMO data valid after SPICLK high (clock polarity = 0) 2 ns
tv(SPCL-SIMO)S High time, SPISIMO data valid after SPICLK low (clock polarity = 1) 2
8 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22 ns
td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+ 27 ns
10 td(SCSL-SOMI)S Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) tc(VCLK) 2tc(VCLK)+trf(SOMI)+ 28 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-6.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
TMS570LS0432 TMS570LS0332 slave_mode_external_timing_phase1_pns160.gifFigure 7-12 SPI Slave Mode External Timing (CLOCK PHASE = 1)
TMS570LS0432 TMS570LS0332 slave_mode_enable_timing_phase1_pns160.gifFigure 7-13 SPI Slave Mode Enable Timing (CLOCK PHASE = 1)