JAJSFJ6C October 2012 – May 2018 TMS570LS0332 , TMS570LS0432
PRODUCTION DATA.
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good I/O signal (PGIO) on the device. During power up or power down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.2.3.1 for the timing information on this glitch filter.
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
VMON | Voltage monitoring thresholds | VCC low - VCC level below this threshold is detected as too low. | 0.75 | 0.9 | 1.13 | V |
VCC high - VCC level above this threshold is detected as too high. | 1.40 | 1.7 | 2.1 | |||
VCCIO low - VCCIO level below this threshold is detected as too low. | 1.85 | 2.4 | 2.9 |