JAJSGD8B October   2018  – Sept 2019 TMUX1574

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーションの例
      2.      ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dynamic Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
      1. 7.8.1 Eye Diagrams
  8. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  IPOFF Leakage Current
    5. 8.5  Transition Time
    6. 8.6  tON (EN) and tOFF (EN) Time
    7. 8.7  tON (VDD) and tOFF (VDD) Time
    8. 8.8  Break-Before-Make Delay
    9. 8.9  Propagation Delay
    10. 8.10 Skew
    11. 8.11 Charge Injection
    12. 8.12 Capacitance
    13. 8.13 Off Isolation
    14. 8.14 Channel-to-Channel Crosstalk
    15. 8.15 Bandwidth
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Beyond Supply Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Powered-off Protection
      5. 9.3.5 Fail-Safe Logic
      6. 9.3.6 Low Capacitance
      7. 9.3.7 Integrated Pull-Down Resistors
    4. 9.4 Device Functional Modes
    5. 9.5 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.12 Capacitance

The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The capacitance is measured in both the on and off state and is denoted by the symbol CON and COFF. Figure 38 shows the setup used to measure capacitance.

TMUX1574 Capacitance.gifFigure 38. Capacitance Measurement Setup