JAJSKO9A March   2020  – March 2021 TMUX4157N

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  Prop Delay
    7. 7.7  Device Turn on Time
    8. 7.8  Charge Injection
    9. 7.9  Off Isolation
    10. 7.10 Crosstalk
    11. 7.11 Bandwidth
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Negative Voltage Input Control for Power Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics


Typical values measured at nominal VSS and TA = 25°C.
PARAMETER TEST CONDITIONS VSS –55°C to 125°C UNIT
MIN TYP MAX
ANALOG SWITCH
RON On-state switch resistance VS = VSS to GND
ISD = 50 mA		 –12 V 1.8 6.5 Ω
–10 V 1.8 6.5
–8 V 1.9 6.5
–6 V 2 6.5
–4 V 2.6 8
RON FLAT On-state switch resistance flatness VS = VSS to GND
ISD = 50 mA		 –12 V 1.8 Ω
–10 V 1.8
–8 V 1.8
–6 V 1.6
–4 V 1.4
ΔRON On-state switch resistance matching between inputs VS = VSS to GND
ISD = 50 mA		 –12 V 0.2 Ω
–10 V 0.2
–8 V 0.25
–6 V 0.25
–4 V 0.3
IS(OFF) Source off-state leakage current Switch Off
VD = VSS / GND
VS = GND / VSS 		–10 V ±1 ±15 µA
ID(ON)
IS(ON) 		Channel on-state leakage current Switch On
VS = VD = GND to VSS 		–10 V ±1 ±15 µA
CSOFF Source off capacitance VS = VSS / 2
f = 1 MHz		 –10 V 10 pF
CSON
CDON 		On capacitance VS = VSS / 2
f = 1 MHz		 –10 V 20 pF
POWER SUPPLY
ISS VSS supply current Logic inputs = GND or 3.3 V
VS = VSS or GND		 –12 V to –4 V 20 70 µA
LOGIC INPUT (SEL)
VIH Input logic high –12 V 1.35 5 V
–10 V 1.35 5
–8 V 1.35 5
–6 V 1.35 5
–4 V 1.35 5
VIL Input logic low –12 V 0 0.8 V
–10 V 0 0.8
–8 V 0 0.8
–6 V 0 0.8
–4 V 0 0.8
IIH
IIL 		Logic input leakage current –12 V to –4 V ±1 ±30 µA
CIN Logic input capacitance –12 V to –4 V 3 pF