JAJSO44A June   2023  – September 2024 TMUX582F-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Global)
    6. 5.6 Single Supply: Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 6.5  Break-Before-Make Delay
    6. 6.6  Enable Delay Time
    7. 6.7  Transition Time
    8. 6.8  Fault Response Time
    9. 6.9  Fault Recovery Time
    10. 6.10 Fault Flag Response Time
    11. 6.11 Fault Flag Recovery Time
    12. 6.12 Charge Injection
    13. 6.13 Off Isolation
    14. 6.14 Crosstalk
    15. 6.15 Bandwidth
    16. 6.16 THD + Noise
  8. 7 Truth Table
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Flat ON- Resistance
      2. 8.2.2 Protection Features
        1. 8.2.2.1 Powered-Off Protection
        2. 8.2.2.2 Fail-Safe Logic
        3. 8.2.2.3 Overvoltage Protection and Detection
        4. 8.2.2.4 Adjacent Channel Operation During Fault
        5. 8.2.2.5 ESD Protection
        6. 8.2.2.6 Latch-Up Immunity
        7. 8.2.2.7 EMC Protection
      3. 8.2.3 Overvoltage Fault Flags
      4. 8.2.4 Bidirectional and Rail-to-Rail Operation
      5. 8.2.5 1.8V Logic Compatible Inputs
      6. 8.2.6 Integrated Pull-Down Resistor on Logic Pins
    3. 8.3 Device Functional Modes
      1. 8.3.1 Normal Mode
      2. 8.3.2 Fault Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 System Diagnostics – Telemetry
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD to VSS Supply voltage  28 V
VDD to GND –0.3 28 V
VSS to GND 0 0 V
VFP to GND Positive fault clamping voltage –0.3 VDD + 0.3 V
VFN to GND Negative fault clamping voltage  0 0 V
VS to GND Source input pin (Sx) voltage to GND 0 65 V
VD Drain pin (D or Dx) voltage 0 VFP+0.7 V
VSEL or VEN Logic control input pin voltage (EN, A0, A1, A2) (2) GND –0.7 28 V
VDIG_OUT Digital output pin (SF, FF) voltage(2) GND –0.7 6 V
ISEL or IEN Logic control input pin current (EN, A0, A1, A2)(2) –30 30 mA
IDIG_OUT Digital output pin (SF, FF) current(2) –10 10 mA
IS or ID (CONT) Source or drain continuous current (Sx or D) IDC ± 10 %(3) IDC ± 10 %(3) mA
Tstg Storage temperature –65 150 °C
TA Ambient temperature –55 150 °C
TJ Junction temperature 150 °C
Ptot(4) Total power dissipation 800 mW
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Stresses have to be kept at or below both voltage and current ratings at all time.
(3) Refer to Recommended Operating Conditions for IDC ratings.
(4) Ptot derates linearly above TA = 70°C by 12.0 mW/°C