JAJSJI8E November   2020  – July 2024 TMUX6208 , TMUX6209

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  36 V Single Supply: Electrical Characteristics 
    9. 6.9  36 V Single Supply: Switching Characteristics 
    10. 6.10 12 V Single Supply: Electrical Characteristics 
    11. 6.11 12 V Single Supply: Switching Characteristics 
    12. 6.12 ±5 V Dual Supply: Electrical Characteristics 
    13. 6.13 ±5 V Dual Supply: Switching Characteristics 
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  tON(EN) and tOFF(EN)
    6. 7.6  Break-Before-Make
    7. 7.7  tON (VDD) Time
    8. 7.8  Propagation Delay
    9. 7.9  Charge Injection
    10. 7.10 Off Isolation
    11. 7.11 Crosstalk
    12. 7.12 Bandwidth
    13. 7.13 THD + Noise
    14. 7.14 Power Supply Rejection Ratio (PSRR)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.6 Latch-Up Immune

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the low impedance path.

The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability.