JAJSLK1A october   2022  – march 2023 TMUX7201 , TMUX7202

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  ±20 V Dual Supply: Electrical Characteristics
    9. 6.9  ±20 V Dual Supply: Switching Characteristics
    10. 6.10 44 V Single Supply: Electrical Characteristics 
    11. 6.11 44 V Single Supply: Switching Characteristics 
    12. 6.12 12 V Single Supply: Electrical Characteristics 
    13. 6.13 12 V Single Supply: Switching Characteristics 
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  tON and tOFF Time
    5. 7.5  tON (VDD) Time
    6. 7.6  Propagation Delay
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Bandwidth
    10. 7.10 THD + Noise
    11. 7.11 Power Supply Rejection Ratio (PSRR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TIA Feedback Gain Switch
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

8.3.7 Ultra-Low Charge Injection

Figure 8-1 shows how the TMUX720x devices have a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

GUID-E509C7FD-0F79-4AD4-9FE9-87F07F01D1E9-low.gif Figure 8-1 Transmission Gate Topology

The TMUX720x contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (S). By design, the excess charge from the switch transition will be pushed into the compensation capacitor on the Source (S) instead of the Drain (D). As a general rule, Cp should be 20x larger than the equivalent load capacitance on the Drain (D). Figure 8-2 shows charge injection variation with different compensation capacitors on the Source side. This plot was captured on the TMUX7219 as part of the TMUX72xx family with a 100 pF load capacitance.

GUID-20210729-CA0I-KVFJ-6WNR-N65GRJM9PQW1-low.svg Figure 8-2 Charge Injection Compensation