JAJSLK1A october   2022  – march 2023 TMUX7201 , TMUX7202

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  ±20 V Dual Supply: Electrical Characteristics
    9. 6.9  ±20 V Dual Supply: Switching Characteristics
    10. 6.10 44 V Single Supply: Electrical Characteristics 
    11. 6.11 44 V Single Supply: Switching Characteristics 
    12. 6.12 12 V Single Supply: Electrical Characteristics 
    13. 6.13 12 V Single Supply: Switching Characteristics 
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  tON and tOFF Time
    5. 7.5  tON (VDD) Time
    6. 7.6  Propagation Delay
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Bandwidth
    10. 7.10 THD + Noise
    11. 7.11 Power Supply Rejection Ratio (PSRR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TIA Feedback Gain Switch
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RQX|8
サーマルパッド・メカニカル・データ
発注情報

6.9 ±20 V Dual Supply: Switching Characteristics

VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted) 
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃  (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
tON Turn-on time from control input VS = 10 V
RL = 300 Ω, CL = 35 pF		 25°C 120 140 ns
–40°C to +85°C 155 ns
–40°C to +125°C 190 ns
tOFF Turn-off time from control input VS = 10 V
RL = 300 Ω, CL = 35 pF		 25°C 120 150 ns
–40°C to +85°C 160 ns
–40°C to +125°C 190 ns
tON (VDD) Device turn on time
(VDD to output)		 VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF		 –40°C to +125°C 0.2 ms
tPD Propagation delay RL = 50 Ω , CL = 5 pF 25°C 400 ps
QINJ Charge injection VS = 0 V, CL = 100 pF 25°C -20 pC
OISO Off-isolation RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz		 25°C –65 dB
OISO Off-isolation RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz		 25°C –45 dB
BW –3 dB Bandwidth RL = 50 Ω , CL = 5 pF
VS = 0 V		 25°C 22 MHz
IL Insertion loss RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz		 25°C –0.10 dB
ACPSRR AC Power Supply Rejection Ratio VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
f = 1 MHz		 25°C –40 dB
THD+N Total Harmonic Distortion + Noise VPP = 20 V, VBIAS = 0 V
RL  =  10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz		 25°C 0.0008 %
CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 42 pF
CD(OFF) Drain off capacitance VS = 0 V, f = 1 MHz 25°C 62 pF
CS(ON),
CD(ON)		 On capacitance VS = 0 V, f = 1 MHz 25°C 240 pF