JAJSLK1A october   2022  – march 2023 TMUX7201 , TMUX7202

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  ±20 V Dual Supply: Electrical Characteristics
    9. 6.9  ±20 V Dual Supply: Switching Characteristics
    10. 6.10 44 V Single Supply: Electrical Characteristics 
    11. 6.11 44 V Single Supply: Switching Characteristics 
    12. 6.12 12 V Single Supply: Electrical Characteristics 
    13. 6.13 12 V Single Supply: Switching Characteristics 
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  tON and tOFF Time
    5. 7.5  tON (VDD) Time
    6. 7.6  Propagation Delay
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Bandwidth
    10. 7.10 THD + Noise
    11. 7.11 Power Supply Rejection Ratio (PSRR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TIA Feedback Gain Switch
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

6.10 44 V Single Supply: Electrical Characteristics 

VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted) 
Typical at VDD = +44 V, VSS = 0 V, TA = 25℃  (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
RON On-resistance VS = 0 V to 40 V
ID = –10 mA
 		 25°C 1.2 1.6 Ω
–40°C to +85°C 2 Ω
–40°C to +125°C 2.4 Ω
RON FLAT On-resistance flatness VS = 0 V to 40 V
ID = –10 mA		 25°C 0.25 0.9 Ω
–40°C to +85°C 1.1 Ω
–40°C to +125°C 1.3 Ω
RON DRIFT On-resistance drift VS = 22 V, IS = –10 mA –40°C to +125°C 0.008 Ω/°C
IS(OFF) Source off leakage current(1) VDD = 44 V, VSS = 0 V
Switch state is off
VS = 40 V / 1 V
VD = 1 V / 40 V		 25°C –1 0.05 1 nA
–40°C to +85°C –10 10 nA
–40°C to +125°C –60 60 nA
ID(OFF) Drain off leakage current(1) VDD = 44 V, VSS = 0 V
Switch state is off
VS = 40 V / 1 V
VD = 1 V / 40 V		 25°C –1 0.05 1 nA
–40°C to +85°C –10 10 nA
–40°C to +125°C –60 60 nA
IS(ON)
ID(ON)		 Channel on leakage current(2) VDD = 44 V, VSS = 0 V
Switch state is on
VS = VD = 40 V or 1 V		 25°C –2 0.05 2 nA
–40°C to +85°C –5 5 nA
–40°C to +125°C –30 30 nA
LOGIC INPUTS (SEL / EN pins)
VIH Logic voltage high –40°C to +125°C 1.3 44 V
VIL Logic voltage low –40°C to +125°C 0 0.8 V
IIH Input leakage current –40°C to +125°C 0.6 2 µA
IIL Input leakage current –40°C to +125°C –0.1 –0.005 µA
CIN Logic input capacitance –40°C to +125°C 3.5 pF
POWER SUPPLY
IDD VDD supply current VDD = 44 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD		 25°C 30 56 µA
–40°C to +85°C 64 µA
–40°C to +125°C   68 µA
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.