SLOS649B March   2010  – May 2016 TPA2026D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Dissipation Ratings
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic Gain Control
        1. 9.3.1.1 Fixed Gain
        2. 9.3.1.2 Limiter Level
        3. 9.3.1.3 Compression Ratio
        4. 9.3.1.4 Interaction Between Compression Ratio and Limiter Range
        5. 9.3.1.5 Noise Gate Threshold
        6. 9.3.1.6 Maximum Gain
        7. 9.3.1.7 Attack, Release, and Hold Time
      2. 9.3.2 Operation With DACS and CODECS
      3. 9.3.3 Short-Circuit Auto-Recovery
      4. 9.3.4 Filter-Free Operation and Ferrite Bead Filters
    4. 9.4 Device Functional Modes
      1. 9.4.1 TPA2026D2 AGC Operation
        1. 9.4.1.1 AGC Start-Up Condition
      2. 9.4.2 TPA2026D2 AGC Recommended Settings
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
      2. 9.5.2 Single and Multiple-Byte Transfers
      3. 9.5.3 Single-Byte Write
      4. 9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.5.5 Single-Byte Read
      6. 9.5.6 Multiple-Byte Read
    6. 9.6 Register Maps
      1. 9.6.1 IC Function Control (Address: 1)
      2. 9.6.2 AGC Attack Control (Address: 2)
      3. 9.6.3 AGC Release Control (Address: 3)
      4. 9.6.4 AGC Hold Time Control (Address: 4)
      5. 9.6.5 AGC Fixed Gain Control (Address: 5)
      6. 9.6.6 AGC Control (Address: 6)
      7. 9.6.7 AGC Control (Address: 7)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2026D2 With Differential Input Signals
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitor
          2. 10.2.1.2.2 Decoupling Capacitor, CS
          3. 10.2.1.2.3 Input Capacitors, CI
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2026D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pad Size
      2. 12.1.2 Component Location
      3. 12.1.3 Trace Width
    2. 12.2 Layout Example
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 YZH Package Dimensions

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

12.1.1 Pad Size

In making the pad size for the WCSP balls, TI recommends that the layout use non solder mask-defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 51 and Table 16 show the appropriate diameters for a WCSP layout. The TPA2026D2 evaluation module (EVM) layout is shown in Layout Example.

TPA2026D2 land_pat_los524.gif Figure 51. Land Pattern Dimensions

Table 16. Land Pattern Dimensions(1) (2) (3) (4)

SOLDER PAD DEFINITIONS COPPER PAD SOLDER MASK(5) OPENING COPPER THICKNESS STENCIL(6) (7) OPENING STENCIL THICKNESS
Non solder mask defined (NSMD) 275 μm
(+0.0, –25 μm)		 375 μm
(+0.0, –25 μm)		 1 oz max (32 μm) 275 μm × 275 μm Sq. (rounded corners) 125 μm thick
(1) Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness must be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness must be less than 20 μm on top of the copper circuit pattern
(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control.
(7) Trace routing away from WCSP device must be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces.

12.1.2 Component Location

Place all external components very close to the TPA2026D2. Placing the decoupling capacitor, CS, close to the TPA2026D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency.

12.1.3 Trace Width

Recommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCB traces. For high current pins (PVDD (L, R), PGND, and audio output pins) of the TPA2026D2, use 100-μm trace widths at the solder balls and at least 500-μm PCB traces to ensure proper performance and output power for the device. For the remaining signals of the TPA2026D2, use 75-μm to 100-μm trace widths at the solder balls. The audio input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation.

12.2 Layout Example

TPA2026D2 layout_ex_SLOS649.gif Figure 52. Layout Recommendation

12.3 Efficiency and Thermal Considerations

The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the package is shown in the dissipation rating table. Converting this to θJA for the DSBGA package:

Equation 7. TPA2026D2 q3_los524.gif

Given θJA of 100°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal dissipation of 0.4 W (0.2 W per channel) for 1.5 W per channel, 8-Ω load, 5-V supply, from Figure 15, the maximum ambient temperature can be calculated with the following equation.

Equation 8. TPA2026D2 q4_los524.gif

Equation 8 shows that the calculated maximum ambient temperature is 110°C at maximum power dissipation with a 5-V supply and 8-Ω a load. The TPA2026D2 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 8-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier.