SLOS649B March   2010  – May 2016 TPA2026D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Dissipation Ratings
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic Gain Control
        1. 9.3.1.1 Fixed Gain
        2. 9.3.1.2 Limiter Level
        3. 9.3.1.3 Compression Ratio
        4. 9.3.1.4 Interaction Between Compression Ratio and Limiter Range
        5. 9.3.1.5 Noise Gate Threshold
        6. 9.3.1.6 Maximum Gain
        7. 9.3.1.7 Attack, Release, and Hold Time
      2. 9.3.2 Operation With DACS and CODECS
      3. 9.3.3 Short-Circuit Auto-Recovery
      4. 9.3.4 Filter-Free Operation and Ferrite Bead Filters
    4. 9.4 Device Functional Modes
      1. 9.4.1 TPA2026D2 AGC Operation
        1. 9.4.1.1 AGC Start-Up Condition
      2. 9.4.2 TPA2026D2 AGC Recommended Settings
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
      2. 9.5.2 Single and Multiple-Byte Transfers
      3. 9.5.3 Single-Byte Write
      4. 9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.5.5 Single-Byte Read
      6. 9.5.6 Multiple-Byte Read
    6. 9.6 Register Maps
      1. 9.6.1 IC Function Control (Address: 1)
      2. 9.6.2 AGC Attack Control (Address: 2)
      3. 9.6.3 AGC Release Control (Address: 3)
      4. 9.6.4 AGC Hold Time Control (Address: 4)
      5. 9.6.5 AGC Fixed Gain Control (Address: 5)
      6. 9.6.6 AGC Control (Address: 6)
      7. 9.6.7 AGC Control (Address: 7)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2026D2 With Differential Input Signals
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitor
          2. 10.2.1.2.2 Decoupling Capacitor, CS
          3. 10.2.1.2.3 Input Capacitors, CI
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2026D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pad Size
      2. 12.1.2 Component Location
      3. 12.1.3 Trace Width
    2. 12.2 Layout Example
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 YZH Package Dimensions

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

YZH Package
16-Pin DSBGA
Top View

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
A1 INR– I Right channel negative audio input
A2 INR+ I Right channel positive audio input
A3 INL+ I Left channel positive audio input
A4 INL– I Left channel negative audio input
B1 AVDD P Analog supply (must be the same as PVDDR and PVDDL)
B2 SCL I I2C clock interface
B3 SDA I/O I2C data interface
B4 AGND P Analog ground (all GND pins need to be connected)
C1 PVDDR P Right channel power supply (must be the same as AVDD and PVDDL)
C2 SDZ I Shutdown terminal (active low)
C3 PGND P Power ground (all GND pins need to be connected)
C4 PVDDL P Left channel power supply (must be the same as AVDD and PVDDR)
D1 OUTR+ O Right channel positive differential output
D2 OUTR– O Right channel negative differential output
D3 OUTL– O Left channel negative differential output
D4 OUTL+ O Left channel positive differential output