JAJS397F August   2009  – July 2016 TPA3111D1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics - VCC = 24 V
    6. 6.6 DC Characteristics - VCC = 12 V
    7. 6.7 AC Characteristics - VCC = 24 V
    8. 6.8 AC Characteristics - VCC = 12 V
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs
      2. 7.3.2 SD Operation
      3. 7.3.3 PLIMIT
      4. 7.3.4 GVDD Supply
      5. 7.3.5 DC Detect
      6. 7.3.6 Short-Circuit Protection and Automatic Recovery Feature
      7. 7.3.7 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPA3111D1 Modulation Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Ferrite Bead Filter Considerations
        2. 8.2.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
        3. 8.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 8.2.2.4 Input Resistance
        5. 8.2.2.5 Input Capacitor, CI
        6. 8.2.2.6 BSN and BSP Capacitors
        7. 8.2.2.7 Differential Inputs
        8. 8.2.2.8 Using Low-ESR Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 8 — Analog supply ground. Connect to the thermal pad.
AVCC 7 P Analog supply. A 100-kΩ resistor in series with AVCC is needed if the PVCC slew rate is greater than
10 V/ms.
AVCC 14 P Connect AVCC supply to this pin.
BSP 17 I Bootstrap I/O for positive high-side FET.
BSP 21 I Bootstrap I/O for positive high-side FET.
BSN 22 I Bootstrap I/O for negative high-side FET.
BSN 26 I Bootstrap I/O for negative high-side FET.
FAULT 2 O Open-drain output used to display short-circuit or DC Detect Fault status. Voltage compliant to AVCC. Short-circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both short-circuit faults and DC Detect Faults must be reset by cycling PVCC.
GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
GND 3 — Connect to local ground
GND 4 — Connect to local ground
GVDD 9 O High-side FET gate drive supply. Nominal voltage is 7 V. Can also be used as supply for PLILMIT divider. Add a 1-µF capacitor to ground at this pin.
INP 12 I Positive audio input. Biased at 3 V.
INN 11 I Negative audio input. Biased at 3 V.
NC 13 — Not connected
OUTP 18 O Class-D H-bridge positive output.
OUTP 20 O Class-D H-bridge positive output.
OUTN 23 O Class-D H-bridge negative output.
OUTN 25 O Class-D H-bridge negative output.
PGND 24 — Power ground for the H-bridges.
PGND 19 — Power ground for the H-bridges.
PLIMIT 10 I Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-µF capacitor to ground at this pin.
PVCC 15 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 16 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 27 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 28 P Power supply for H-bridge. PVCC pins are also connected internally.
SD 1 I Shutdown logic input for audio amplifier (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.