JAJSCV9C May   2016  – January 2018 TPA3128D2 , TPA3129D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーションの簡略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Gain Setting and Master and Slave
      2. 7.3.2  Input Impedance
      3. 7.3.3  Startup and Shutdown Operation
      4. 7.3.4  PLIMIT Operation
      5. 7.3.5  GVDD Supply
      6. 7.3.6  BSPx AND BSNx Capacitors
      7. 7.3.7  Differential Inputs
      8. 7.3.8  Device Protection System
      9. 7.3.9  DC Detect Protection
      10. 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 7.3.11 Thermal Protection
      12. 7.3.12 Device Modulation Scheme
        1. 7.3.12.1 BD-Modulation
      13. 7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 7.3.14 Ferrite Bead Filter Considerations
      15. 7.3.15 When to Use an Output Filter for EMI Suppression
      16. 7.3.16 AM Avoidance EMI Reduction
    4. 7.4 Device Functional Modes
      1. 7.4.1 PBTL Mode
      2. 7.4.2 Mono Mode (Single Channel Mode)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requriements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the PWM Frequency
        2. 8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
        3. 8.2.2.3 Select Input Capacitance
        4. 8.2.2.4 Select Decoupling Capacitors
        5. 8.2.2.5 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 DC Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω, fs = 400 kHz, low idle-loss mode(unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V 1.5 5 mV
ICC Quiescent supply current SDZ = 2 V, With load and filter, PVCC = 12 V 17 mA
SDZ = 2 V, With load and filter, PVCC = 24 V 23 mA
ICC(SD) Quiescent supply current in shutdown mode SDZ = 0.8 V, With load and filter, PVCC = 12 V 20 µA
SDZ = 0.8 V, With load and filter, PVCC = 24 V 30
rDS(on) Drain-source on-state resistance, measured pin to pin PVCC = 21 V, Iout = 500 mA, TJ = 25°C 90 mΩ
G Gain (BTL) R1 = 5.6 kΩ, R2 = Open 19 20 21 dB
R1 = 20 kΩ, R2 = 100 kΩ 25 26 27
R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 dB
R1 = 47 kΩ, R2 = 75 kΩ 35 36 37
G Gain (SLV) R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 dB
R1 = 75 kΩ, R2 = 47 kΩ 25 26 27
R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 dB
R1 = 100 kΩ, R2 = 16 kΩ 35 36 37
ton Turn-on time SDZ = 2 V 40 ms
tOFF Turn-off time SDZ = 0.8 V 2 µs
GVDD Gate drive supply IGVDD < 200 µA 5.1 5.6 6.3 V
VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 8.2 8.75 V