JAJSCV9C
May 2016 – January 2018
TPA3128D2
,
TPA3129D2
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
アプリケーションの簡略回路図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Gain Setting and Master and Slave
7.3.2
Input Impedance
7.3.3
Startup and Shutdown Operation
7.3.4
PLIMIT Operation
7.3.5
GVDD Supply
7.3.6
BSPx AND BSNx Capacitors
7.3.7
Differential Inputs
7.3.8
Device Protection System
7.3.9
DC Detect Protection
7.3.10
Short-Circuit Protection and Automatic Recovery Feature
7.3.11
Thermal Protection
7.3.12
Device Modulation Scheme
7.3.12.1
BD-Modulation
7.3.13
Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
7.3.14
Ferrite Bead Filter Considerations
7.3.15
When to Use an Output Filter for EMI Suppression
7.3.16
AM Avoidance EMI Reduction
7.4
Device Functional Modes
7.4.1
PBTL Mode
7.4.2
Mono Mode (Single Channel Mode)
8
Applications and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requriements
8.2.2
Detailed Design Procedure
8.2.2.1
Select the PWM Frequency
8.2.2.2
Select the Amplifier Gain and Master/Slave Mode
8.2.2.3
Select Input Capacitance
8.2.2.4
Select Decoupling Capacitors
8.2.2.5
Select Bootstrap Capacitors
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Power Supply Mode
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントのサポート
11.2
コミュニティ・リソース
11.3
商標
11.4
静電気放電に関する注意事項
11.5
Glossary
12
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DAP|32
MPDS380A
サーマルパッド・メカニカル・データ
DAP|32
PPTD001K
発注情報
jajscv9c_oa
jajscv9c_pm
6.7
Typical Characteristics
f
s
= 400 kHz, Ultra Low Idle Loss Mode, TPA3128D2EVM Tested With AP2722. (unless otherwise noted)
Figure 1.
Idle Current vs PVCC
Figure 3.
Total Harmonic Distortion + Noise (BTL) vs Frequency
Figure 5.
Total Harmonic Distortion + Noise (BTL) vs Output Power
Figure 7.
Total Harmonic Distortion + Noise (BTL) vs Output Power
Figure 9.
Output Power (BTL) vs Plimit Voltage
Figure 11.
Maximum Output Power (BTL) vs Supply Voltage
Figure 13.
Power Efficiency (BTL) vs Output Power
Figure 15.
Crosstalk vs Frequency
Figure 17.
Supply Ripple Rejection Ratio (BTL) vs Frequency
Figure 19.
Total Harmonic Distortion + Noise (PBTL) vs Output Power
Figure 21.
Power Efficiency (PBTL) vs Output Power
Figure 23.
Total Harmonic Distortion + Noise (PBTL) vs Output Power
Figure 2.
Total Harmonic Distortion + Noise (BTL) vs Frequency
Figure 4.
Total Harmonic Distortion + Noise (BTL) vs Output Power
Figure 6.
Total Harmonic Distortion + Noise (BTL) vs Output Power
Figure 8.
Total Harmonic Distortion + Noise (BTL) vs Output Power
Figure 10.
Gain/Phase (BTL) vs Frequency
Figure 12.
Maximum Output Power (BTL) vs Supply Voltage
Figure 14.
Power Efficiency (BTL) vs Output Power
Figure 16.
Crosstalk vs Frequency
Figure 18.
Total Harmonic Distortion + Noise (PBTL) vs Frequency
Figure 20.
Maximum Output Power (PBTL) vs Supply Voltage
Figure 22.
Supply Ripple Rejection Ratio (PBTL) vs Frequency
Figure 24.
Maximum Output Power (PBTL) vs Supply Voltage