JAJSC84F May   2016  – January 2020 TPA3136AD2 , TPA3136D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Fixed Analog Gain
      2. 10.3.2 SD Operation
      3. 10.3.3 PLIMIT
      4. 10.3.4 Spread Spectrum and De-Phase Control
      5. 10.3.5 GVDD Supply
      6. 10.3.6 DC Detect
      7. 10.3.7 PBTL Select
      8. 10.3.8 Short-Circuit Protection and Automatic Recovery Feature
      9. 10.3.9 Thermal Protection
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 PCB Material Recommendation
        2. 11.2.1.2 PVCC Capacitor Recommendation
        3. 11.2.1.3 Decoupling Capacitor Recommendations
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Ferrite Bead Filter Considerations
        2. 11.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 11.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 11.2.2.4 Input Resistance
        5. 11.2.2.5 Input Capacitor, Ci
        6. 11.2.2.6 BSN and BSP Capacitors
        7. 11.2.2.7 Differential Inputs
        8. 11.2.2.8 Using Low-ESR Capacitors
      3. 11.2.3 Application Performance Curves
        1. 11.2.3.1 EN55013 Radiated Emissions Results
        2. 11.2.3.2 EN55022 Conducted Emissions Results
  12. 12Power Supply Recommendations
    1. 12.1 Power Supply Decoupling, CS
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 14.2 ドキュメントのサポート
      1. 14.2.1 関連資料
    3. 14.3 関連リンク
    4. 14.4 ドキュメントの更新通知を受け取る方法
    5. 14.5 サポート・リソース
    6. 14.6 商標
    7. 14.7 静電気放電に関する注意事項
    8. 14.8 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.7 Typical Characteristics

All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
TPA3136D2 TPA3136AD2 D001_SLOS938_TPA3136.gif
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 1 W, 2.5 W, 5 W
Figure 1. Total Harmonic Distortion vs Frequency (BTL)
TPA3136D2 TPA3136AD2 D003_SLOS938_TPA3136.gif
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 20 Hz, 1 kHz
Figure 3. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3136D2 TPA3136AD2 D005_SLOS938_TPA3136.gif
AVCC=PVCC = 4.5 V to 14.4 V, Load = 6 Ω + 47 µH
Figure 5. Output Power vs Supply Voltage (BTL)
TPA3136D2 TPA3136AD2 D007_SLOS938_TPA3136.gif
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH (device pins)
Figure 7. Gain/Phase vs Frequency (BTL)
TPA3136D2 TPA3136AD2 D009_SLOS938_TPA3136.gif
AVCC=PVCC= 6 V, 13 V, 14.4 V, Load = 8 Ω + 66 µH
Figure 9. Efficiency vs Output Power (BTL)
TPA3136D2 TPA3136AD2 D011_SLOS938_TPA3136.gif
AVCC=PVCC = 12 V, Load = 4 Ω + 33 µH
Figure 11. Supply Ripple Rejection Ratio vs Frequency (BTL)
TPA3136D2 TPA3136AD2 D013_SLOS938_TPA3136.gif
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 20 Hz, 1 kHz
Figure 13. Total Harmonic Distortion + Noise vs Output Power (PBTL)
TPA3136D2 TPA3136AD2 D015_SLOS938_TPA3136.gif
AVCC=PVCC = 6 V, 13 V, 14.4 V, Load = 4 Ω + 33 µH
Figure 15. Efficiency vs Output Power (PBTL)
TPA3136D2 TPA3136AD2 D002_SLOS938_TPA3136.gif
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 1 W, 2.5 W, 5 W
Figure 2. Total Harmonic Distortion vs Frequency (BTL)
TPA3136D2 TPA3136AD2 D004_SLOS938_TPA3136.gif
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 20 Hz, 1 kHz
Figure 4. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3136D2 TPA3136AD2 D006_SLOS938_TPA3136.gif
AVCC=PVCC = 4.5 V to 14.4 V, Load = 8 Ω + 66 µH
Figure 6. Output Power vs Supply Voltage (BTL)
TPA3136D2 TPA3136AD2 D008_SLOS938_TPA3136.gif
AVCC=PVCC = 6 V, 12 V, 14.4 V, Load = 6 Ω + 47 µH
Figure 8. Efficiency vs Output Power (BTL)
TPA3136D2 TPA3136AD2 D010_SLOS938_TPA3136.gif
AVCC=PVCC = 12 V, 1 W, Load = 6 Ω + 47 µH
Figure 10. Crosstalk vs Frequency (BTL)
TPA3136D2 TPA3136AD2 D012_SLOS938_TPA3136.gif
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 1 W, 2.5 W, 5 W
Figure 12. Total Harmonic Distortion + Noise vs Frequency (PBTL)
TPA3136D2 TPA3136AD2 D014_SLOS938_TPA3136.gif
AVCC=PVCC = 4.5 V to 14.4 V, Load = 4 Ω + 33 µH
Figure 14. Output Power vs Supply Voltage (PBTL)