JAJSC84F May   2016  – January 2020 TPA3136AD2 , TPA3136D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Fixed Analog Gain
      2. 10.3.2 SD Operation
      3. 10.3.3 PLIMIT
      4. 10.3.4 Spread Spectrum and De-Phase Control
      5. 10.3.5 GVDD Supply
      6. 10.3.6 DC Detect
      7. 10.3.7 PBTL Select
      8. 10.3.8 Short-Circuit Protection and Automatic Recovery Feature
      9. 10.3.9 Thermal Protection
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 PCB Material Recommendation
        2. 11.2.1.2 PVCC Capacitor Recommendation
        3. 11.2.1.3 Decoupling Capacitor Recommendations
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Ferrite Bead Filter Considerations
        2. 11.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 11.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 11.2.2.4 Input Resistance
        5. 11.2.2.5 Input Capacitor, Ci
        6. 11.2.2.6 BSN and BSP Capacitors
        7. 11.2.2.7 Differential Inputs
        8. 11.2.2.8 Using Low-ESR Capacitors
      3. 11.2.3 Application Performance Curves
        1. 11.2.3.1 EN55013 Radiated Emissions Results
        2. 11.2.3.2 EN55022 Conducted Emissions Results
  12. 12Power Supply Recommendations
    1. 12.1 Power Supply Decoupling, CS
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 14.2 ドキュメントのサポート
      1. 14.2.1 関連資料
    3. 14.3 関連リンク
    4. 14.4 ドキュメントの更新通知を受け取る方法
    5. 14.5 サポート・リソース
    6. 14.6 商標
    7. 14.7 静電気放電に関する注意事項
    8. 14.8 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.7 PBTL Select

The TPA3136D2, TPA3136AD2 device offers the feature of parallel BTL operation with two outputs of each channel connected directly. If the PBTL (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, tie PBTL pin to VCC and apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and RIGHT outputs with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half bridges for highest power efficiency. For an example of the PBTL connection, see the schematic in the Typical Applications section.