JAJSC84F May   2016  – January 2020 TPA3136AD2 , TPA3136D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Fixed Analog Gain
      2. 10.3.2 SD Operation
      3. 10.3.3 PLIMIT
      4. 10.3.4 Spread Spectrum and De-Phase Control
      5. 10.3.5 GVDD Supply
      6. 10.3.6 DC Detect
      7. 10.3.7 PBTL Select
      8. 10.3.8 Short-Circuit Protection and Automatic Recovery Feature
      9. 10.3.9 Thermal Protection
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 PCB Material Recommendation
        2. 11.2.1.2 PVCC Capacitor Recommendation
        3. 11.2.1.3 Decoupling Capacitor Recommendations
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Ferrite Bead Filter Considerations
        2. 11.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 11.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 11.2.2.4 Input Resistance
        5. 11.2.2.5 Input Capacitor, Ci
        6. 11.2.2.6 BSN and BSP Capacitors
        7. 11.2.2.7 Differential Inputs
        8. 11.2.2.8 Using Low-ESR Capacitors
      3. 11.2.3 Application Performance Curves
        1. 11.2.3.1 EN55013 Radiated Emissions Results
        2. 11.2.3.2 EN55022 Conducted Emissions Results
  12. 12Power Supply Recommendations
    1. 12.1 Power Supply Decoupling, CS
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 14.2 ドキュメントのサポート
      1. 14.2.1 関連資料
    3. 14.3 関連リンク
    4. 14.4 ドキュメントの更新通知を受け取る方法
    5. 14.5 サポート・リソース
    6. 14.6 商標
    7. 14.7 静電気放電に関する注意事項
    8. 14.8 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP
(Top View)

Pin Functions

PIN I/O/P(1) DESCRIPTION
NAME NUMBER
SD 1 I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
FAULT 2 O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC.
LINP 3 I Positive audio input for left channel. Biased at 3 V.
LINN 4 I Negative audio input for left channel. Biased at 3 V.
NC 5, 6, 13 I No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.
AVCC 7 P Analog supply
GND 8 P Analog signal ground.
GVDD 9 O High-side FET gate drive supply. Nominal voltage is 7 V.
PLIMIT 10 I Power Limiter Control pin
RINN 11 I Negative audio input for right channel. Biased at 3 V.
RINP 12 I Positive audio input for right channel. Biased at 3 V.
PBTL 14 I Parallel BTL mode select pin. L=Stereo BTL mode, H=Mono PBTL mode
PVCC 15, 16 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally.
BSPR 17 I Bootstrap I/O for right channel, positive high-side FET.
OUTPR 18 O Class-D H-bridge positive output for right channel.
GND 19 P Power ground for the H-bridges.
OUTNR 20 O Class-D H-bridge negative output for right channel.
BSNR 21 I Bootstrap I/O for right channel, negative high-side FET.
BSNL 22 I Bootstrap I/O for left channel, negative high-side FET.
OUTNL 23 O Class-D H-bridge negative output for left channel.
GND 24 P Power ground for the H-bridges.
OUTPL 25 O Class-D H-bridge positive output for left channel.
BSPL 26 I Bootstrap I/O for left channel, positive high-side FET.
PVCC 27, 28 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally.
Thermal Pad P Connect to GND for best thermal and electrical performance.
(1) I = Input, O = Output, P = Power