JAJSC84F May   2016  – January 2020 TPA3136AD2 , TPA3136D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Fixed Analog Gain
      2. 10.3.2 SD Operation
      3. 10.3.3 PLIMIT
      4. 10.3.4 Spread Spectrum and De-Phase Control
      5. 10.3.5 GVDD Supply
      6. 10.3.6 DC Detect
      7. 10.3.7 PBTL Select
      8. 10.3.8 Short-Circuit Protection and Automatic Recovery Feature
      9. 10.3.9 Thermal Protection
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 PCB Material Recommendation
        2. 11.2.1.2 PVCC Capacitor Recommendation
        3. 11.2.1.3 Decoupling Capacitor Recommendations
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Ferrite Bead Filter Considerations
        2. 11.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 11.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 11.2.2.4 Input Resistance
        5. 11.2.2.5 Input Capacitor, Ci
        6. 11.2.2.6 BSN and BSP Capacitors
        7. 11.2.2.7 Differential Inputs
        8. 11.2.2.8 Using Low-ESR Capacitors
      3. 11.2.3 Application Performance Curves
        1. 11.2.3.1 EN55013 Radiated Emissions Results
        2. 11.2.3.2 EN55022 Conducted Emissions Results
  12. 12Power Supply Recommendations
    1. 12.1 Power Supply Decoupling, CS
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 14.2 ドキュメントのサポート
      1. 14.2.1 関連資料
    3. 14.3 関連リンク
    4. 14.4 ドキュメントの更新通知を受け取る方法
    5. 14.5 サポート・リソース
    6. 14.6 商標
    7. 14.7 静電気放電に関する注意事項
    8. 14.8 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage AVCC to GND, PVCC to GND –0.3 20 V
Input current To any pin except supply pins 10 mA
Voltage SD, FAULT to GND(2) –0.3 AVCC + 0.3 V
10 V/ms
Voltage RINN, RINP, LINN, LINP –0.3 6.3 V
Minimum load resistance, RL BTL, PVCC > 12 V 4.8 Ω
BTL, PVCC ≤ 12 V 3.2
PBTL, PVCC > 12 V 2.5
PBTL, PVCC ≤ 12 V 1.8
Continuous total power dissipation See the Thermal Information Table
Operating free-air temperature range, TA(3) –40 85 °C
Temperature range –65 150 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series with the pins.
(3) The TPA3136D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.