JAJSEX8A March   2018  – June 2018 TPA3138D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      フェライト・ビーズ付きのTPA3138のレイアウト
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Gain
      2. 9.3.2  SD/FAULT Operation
      3. 9.3.3  PLIMIT
      4. 9.3.4  Spread Spectrum and De-Phase Control
      5. 9.3.5  GVDD Supply
      6. 9.3.6  DC Detect
      7. 9.3.7  PBTL Select
      8. 9.3.8  Short-Circuit Protection and Automatic Recovery Feature
      9. 9.3.9  Over-Temperature Protection (OTP)
      10. 9.3.10 Over-Voltage Protection (OVP)
      11. 9.3.11 Under-Voltage Protection (UVP)
    4. 9.4 Device Functional Modes
      1. 9.4.1 MODE_SEL = LOW: BD Modulation
      2. 9.4.2 MODE_SEL = HIGH: Low-Idle-Current 1SPW Modulation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 PCB Material Recommendation
        2. 10.2.1.2 PVCC Capacitor Recommendation
        3. 10.2.1.3 Decoupling Capacitor Recommendations
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Ferrite Bead Filter Considerations
        2. 10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 10.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 10.2.2.4 Input Resistance
        5. 10.2.2.5 Input Capacitor, Ci
        6. 10.2.2.6 BSN and BSP Capacitors
        7. 10.2.2.7 Differential Inputs
        8. 10.2.2.8 Using Low-ESR Capacitors
      3. 10.2.3 Application Performance Curves
        1. 10.2.3.1 EN55013 Radiated Emissions Results
        2. 10.2.3.2 EN55022 Conducted Emissions Results
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling, CS
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω. Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC CHARACTERISTICS
PSRR Power supply ripple rejection 200-mVPP ripple at 1 kHz,
Gain = 26 dB, Inputs ac-coupled to GND		 –70 dB
PO Continuous output power, BTL THD+N = 1%, f = 1 kHz, PVCC = 12 V, RL = 6 Ω 10 W
PO Continuous output power, BTL THD+N = 10%, f = 1 kHz, PVCC = 12 V, RL = 6 Ω 12 W
PO Continuous output power, BTL THD+N = 1%, f = 1 kHz, PVCC = 12 V, RL = 8 Ω 8 W
PO Continuous output power, BTL THD+N = 10%, f = 1 kHz, PVCC = 12 V, RL = 8 Ω 9.9 W
PO Continuous output power, PBTL (mono) THD+N = 10%, f = 1 kHz, PVCC = 12 V, RL = 4 Ω 18.5 W
IO Maximum output current f = 1 kHz, RL = 3 Ω 3.5 A
THD+N Total harmonic distortion + noise f = 1 kHz, PO = 5 W (half-power) 0.04 %
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 26 dB 85 µV
–81 dBV
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 72 µV
-82.6 dBV
Crosstalk VO = 1 Vrms, Gain = 26 dB, f = 1 kHz -95 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%,
f = 1 kHz, Gain = 26 dB, A-weighted		 102 dB
OTE Thermal trip point 150 °C
Thermal hysteresis 15 °C
DC CHARACTERISTICS
| VOS | Output offset voltage
(measured differentially)		 VI = 0 V, Gain = 26 dB 1.5 mV
ICC Quiescent supply current SD/FAULT = 2 V, 10 µF + 680 nF output filter,
1SPW Mode, PVCC = 12 V		 20 mA
ICC Quiescent supply current SD/FAULT = 2 V, 10 µF + 680 nF output filter, 
BD Mode, PVCC = 12 V		   37 mA
ICC(SD) Quiescent supply current in shutdown mode SD/FAULT = 0.8 V, no load 10 µA
rDS(on) Drain-source on-state resistance IO = 500 mA, TJ = 25°C
excluding metal and bond wire resistance		 High Side 180 mΩ
Low side 180
G Gain GAIN_SEL= 0.8 V 19 20 21 dB
G Gain GAIN_SEL= 2 V 25 26 27 dB
tON Turn-on time SD/FAULT = 2 V 50 ms
tOFF Turn-off time SD/FAULT = 0.8 V 2.9 µs
GVDD Gate drive supply IGVDD = 2 mA 4.8 5 5.2 V
tDCDET DC detect time VRINP = 2.6 V and VRINN = 2.4 V,
or VRINP = 2.4 V and VRINN = 2.6 V		 800 ms
OVP Over Voltage Protection 15.8 V
UVP Under Voltage Protection MODE_SEL = 0.8 V (BD mode) 7.5 V
UVP Under Voltage Protection MODE_SEL = 2 V, or floating (1SPW mode) 3.4 V