JAJSI28A October   2019  – August 2020 TPA3139D2

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics,
      1. 6.7.1 Bridge -Tied Load (BTL)
      2. 6.7.2 Paralleled Bridge -Tied Load (PBTL)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Gain
      2. 7.3.2  SD/ FAULT and MUTE Operation
      3. 7.3.3  PLIMIT
      4. 7.3.4  Spread Spectrum and De-Phase Control
      5. 7.3.5  GVDD Supply
      6. 7.3.6  DC Detect
      7. 7.3.7  PBTL Select
      8. 7.3.8  Short-Circuit Protection and Automatic Recovery Feature
      9. 7.3.9  Over-Temperature Protection (OTP)
      10. 7.3.10 Over-Voltage Protection (OVP)
      11. 7.3.11 Under-Voltage Protection (UVP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE_SEL = LOW: BD Modulation
      2. 7.4.2 MODE_SEL = HIGH: Low-Idle-Current 1SPW Modulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 PCB Material Recommendation
        2. 8.2.1.2 PVCC Capacitor Recommendation
        3. 8.2.1.3 Decoupling Capacitor Recommendations
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Ferrite Bead Filter Considerations
        2. 8.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 8.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 8.2.2.4 Input Resistance
        5. 8.2.2.5 Input Capacitor, Ci
        6. 8.2.2.6 BSN and BSP Capacitors
        7. 8.2.2.7 Differential Inputs
        8. 8.2.2.8 Using Low-ESR Capacitors
      3. 8.2.3 Application Performance Curves
        1. 8.2.3.1 EN55013 Radiated Emissions Results
        2. 8.2.3.2 EN55022 Conducted Emissions Results
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling, CS
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Pin Functions

PINI/O/P(1)DESCRIPTION
NAMENO.
OUTPL1OClass-D H-bridge positive output for left channel.
BSPL2PBootstrap supply (BST) for positive high-side FET of the left channel.
PVCCL3PPower supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally.
SD/FAULT4IOTTL logic levels with compliance to AVCC. Shutdown logic input for audio amp (LOW, outputs Hi-Z; HIGH, outputs enabled). General fault reporting includes Over-Temp, Over-Current, and DC Detect. SD/ FAULT= High, normal operation, SD/ FAULT= Low, fault condition. Device will auto-recover once the OT/OC/DC Fault has been removed.
LINP5IPositive audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.
LINN6INegative audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode.
GAIN_SEL7IGain select least significant bit. TTL logic levels with compliance to AVDD. Low = 20-dB Gain, High = 26-dB Gain, Floating = 26-dB Gain.
MODE_SEL8IMode select least significant bit. TTL logic levels with compliance to AVDD. Low = BD Mode with UV Threshold = 7.5 V, High = 1SPW Mode with UV Threshold = 3.4V, Floating = 1SPW Mode with UV threshold = 3.4V.
AVCC9PAnalog supply.
AGND10PAnalog signal ground.
GVDD11OFET gate drive supply. Nominal voltage is 5 V.
PLIMIT12IPower limiter level control. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
RINN13INegative audio input for right channel. Biased at 2.5 V.
RINP14IPositive audio input for right channel. Biased at 2.5 V.
MUTE15IMute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC.
PVCCR16PPower supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally.
BSPR17PBootstrap supply (BST) for positive high-side FET of the right channel.
OUTPR18OClass-D H-bridge positive output for right channel.
PGND19PPower ground for the H-bridges.
OUTNR20OClass-D H-bridge negative output for right channel.
BSNR21PBootstrap supply (BST) for negative high-side FET of the right channel.
BSNL22PBootstrap supply (BST) for negative high-side FET of the left channel.
OUTNL23OClass-D H-bridge negative output for left channel.
PGND24PPower ground for the H-bridges.
Thermal PadPConnect to GND for best thermal and electrical performance
(1) I = Input, O = Output, IO = Input and Output, P = Power