JAJSO54 November   2022 TPA3223

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  7. 7 Specifications
    1. 7.1 絶対最大定格
    2. 7.2 ESD 定格
    3. 7.3 推奨動作条件
    4. 7.4 熱に関する情報
    5. 7.5 電気的特性
    6. 7.6 オーディオ特性 (BTL)
    7. 7.7 オーディオ特性 (PBTL)
    8. 7.8 Typical Characteristics, BTL Configuration, AD-mode
    9. 7.9 Typical Characteristics, PBTL Configuration, AD-mode
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Input Configuration, Gain Setting And Primary / Peripheral Operation
      2. 9.3.2 Gain Setting And Clock Synchronization
      3. 9.3.3 PWM Modulation
      4. 9.3.4 Oscillator
      5. 9.3.5 Input Impedance
      6. 9.3.6 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Powering Up
        1. 9.4.1.1 Startup Ramp Time
      2. 9.4.2 Powering Down
        1. 9.4.2.1 Power Down Ramp Time
      3. 9.4.3 Device Reset
      4. 9.4.4 Device Soft Mute
      5. 9.4.5 Device Protection System
        1. 9.4.5.1 Overload and Short Circuit Current Protection
        2. 9.4.5.2 Signal Clipping and Pulse Injector
        3. 9.4.5.3 DC Speaker Protection
        4. 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.5.5 Overtemperature Protection OTW and OTE
        6. 9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP), and Power-on Reset (POR)
        7. 9.4.5.7 Fault Handling
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 BST capacitors
          4. 10.2.1.2.4 PCB Material Recommendation
      2. 10.2.2 Application Curves
      3. 10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 10.2.3.1 Design Requirements
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power Supplies
        1. 10.3.1.1 VDD Supply
        2. 10.3.1.2 AVDD and GVDD Supplies
        3. 10.3.1.3 PVDD Supply
        4. 10.3.1.4 BST Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
        1. 10.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 10.4.2.2 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Pin Functions

Table 6-1 Pin Functions Table
NAMENO.I/O(1)DESCRIPTION
AVDD2PAVDD voltage supply. Refer to: Section 10.3.1.2
BST1_M24POUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required.
Refer to: Section 10.2.1.2.3
BST1_P23POUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required.
Refer to: Section 10.2.1.2.3
BST2_M44POUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required.
Refer to: Section 10.2.1.2.3
BST2_P43POUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required.
Refer to: Section 10.2.1.2.3
CMUTE6PMute and Startup Timing Capacitor. Connect a 33 nF capacitor to GND. Refer to: Section 9.4.3
FAULT19OShutdown signal, open drain; active low. Refer to: Section 9.3.6
FREQ_ADJ9OOscillator frequency programming pin. Refer to: Section 9.3.4
GAIN/CLKSYNC21IClosed loop gain and clock synchronization configuration pin.
Refer to: Section 9.3.1
GND4,5,12,16,25,26,42,33,34,41PGround
GVDD1PGate drive supply. Refer to: Section 10.3.1.2
IN1_M14INegative audio input for channel 1
IN1_P15IPositive audio input for channel 1
IN2_M7INegative audio input for channel 2
IN2_P8IPositive audio input for channel 2
NC 3,17,18 Not connected or pulled to ground
OSCM11I/OOscillator synchronization interface.
Refer to: Section 9.3.1
OSCP10I/OOscillator synchronization interface.
Refer to: Section 9.3.1
OTW_CLIP20OClipping warning and Over-temperature warning; open drain; active low.
Refer to: Section 9.3.6
OUT1_M32ONegative output for channel 1
OUT1_P27,28OPositive output for channel 1
OUT2_M39,40ONegative output for channel 2
OUT2_P35OPositive output for channel 2
PVDD29,30,31,36,37,38PPVDD supply. Refer to: Section 10.2.1.2.2 and Section 10.3.1.3
RESET13IDevice reset input; active low. Refer to: Section 9.4.5.7, Section 9.4.1, Section 9.4.2
VDD22PInput power supply. Refer to: Section 10.3.1.1
PowerPad™PGround, connect to grounded heatsink. Placed on top side of device.
(1) I=Input, O=Output, I/O= Input/Output, P=Power
Table 6-2 Mode Selection Pins
MODE PINS(2)INPUT MODE(1)OUTPUT CONFIGURATIONDESCRIPTION
IN2_MIN2_P
XX1N/2N + 12 × BTLStereo, BTL output configuration, AD mode modulation
001N/2N + 11 x PBTLMono, Paralleled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation
111N/2N + 11 x BTLMono, BTL configuration. OUT1_M and OUT1_P active, AD mode modulation
(1) 2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control ( RESET) input pins.
(2) X refers to inputs connected through AC coupling capacitor, 0 refers to logic low (GND), 1 refers to logic high (AVDD).