TPA3223 はフルパワー、アイドル、およびスタンバイ状態での効率的な動作を実現するハイパワー Class-D アンプです。閉ループ帰還を特長としているため、音声帯域全体の歪みが小さく、優れたサウンドを提供します。このデバイスは AD 変調で動作し、4Ω の負荷に最大 2 x 200W、2Ω の負荷に最大 1 x 400W の出力を駆動できます。
TPA3223 は、最大 2VRMS をサポートするシングルエンドまたは差動アナログ入力インターフェイスを備えており、4 つのゲインを選択できます。20dB、23.5dB、32dB、36dB.また、TPA3223 は 90% を上回る高効率を達成しており、アイドル時の消費電力が低いだけでなく、スタンバイ時の消費電力も極めて低くなっています (0.1W 未満)。これは、60mΩ の MOSFET、最適化されたゲート・ドライブ方式、および低消費電力の動作モードを採用することで可能となりました。設計をさらに簡素化するため、低電圧、過電圧、サイクル単位の電流制限、短絡、クリッピング検出、過熱警告およびシャットダウン、DC スピーカー保護といった必須の保護機能も統合されています。
部品番号 | パッケージ | 本体サイズ (公称) |
---|---|---|
TPA3223 | HTSSOP (44) | 6.10mm×14.00mm |
DATE | REVISION | NOTES |
---|---|---|
November 2022 | * | Initial release |
DEVICE NAME | DESCRIPTION | SUPPLY VOLTAGE | THERMAL PAD LOCATION |
---|---|---|---|
TPA3220 | 60-W Stereo, 110-W Peak HD Analog-Input, Pad-Down Class-D Amplifier | 32 V | Bottom |
TPA3221 | 100 W Stereo, 200 W Mono HD, Analog-Input, Class-D Amplifier | 32 V | Top |
TPA3244 | 60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier | 31.5 V | Bottom |
TPA3245 | 115-W Stereo, 230-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier | 31.5 V | Top |
TPA3250 | 70 W Stereo, 130 W Peak Ultra-HD, Analog-Input, Pad-Down Class-D Amplifier | 38 V | Bottom |
TPA3251 | 175 W Stereo, 350 W Mono Ultra-HD, Analog-Input Class-D Amplifier | 38 V | Top |
TPA3255 | 315 W Stereo, 600 W Mono Ultra-HD, Analog-Input Class-D Amplifier | 53.5 V | Top |
The TPA3223 is available in a thermally enhanced TSSOP package.
The package type contains a thermal pad that is located on the top side of the device for convenient thermal coupling to the heat sink.
NAME | NO. | I/O(1) | DESCRIPTION |
---|---|---|---|
AVDD | 2 | P | AVDD voltage supply. Refer to: Section 10.3.1.2 |
BST1_M | 24 | P | OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required. Refer to: Section 10.2.1.2.3 |
BST1_P | 23 | P | OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required. Refer to: Section 10.2.1.2.3 |
BST2_M | 44 | P | OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required. Refer to: Section 10.2.1.2.3 |
BST2_P | 43 | P | OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required. Refer to: Section 10.2.1.2.3 |
CMUTE | 6 | P | Mute and Startup Timing Capacitor. Connect a 33 nF capacitor to GND. Refer to: Section 9.4.3 |
FAULT | 19 | O | Shutdown signal, open drain; active low. Refer to: Section 9.3.6 |
FREQ_ADJ | 9 | O | Oscillator frequency programming pin. Refer to: Section 9.3.4 |
GAIN/CLKSYNC | 21 | I | Closed loop gain and clock synchronization configuration pin. Refer to: Section 9.3.1 |
GND | 4,5,12,16,25,26,42,33,34,41 | P | Ground |
GVDD | 1 | P | Gate drive supply. Refer to: Section 10.3.1.2 |
IN1_M | 14 | I | Negative audio input for channel 1 |
IN1_P | 15 | I | Positive audio input for channel 1 |
IN2_M | 7 | I | Negative audio input for channel 2 |
IN2_P | 8 | I | Positive audio input for channel 2 |
NC | 3,17,18 | Not connected or pulled to ground | |
OSCM | 11 | I/O | Oscillator synchronization interface. Refer to: Section 9.3.1 |
OSCP | 10 | I/O | Oscillator synchronization interface. Refer to: Section 9.3.1 |
OTW_CLIP | 20 | O | Clipping warning and Over-temperature warning; open drain; active low. Refer to: Section 9.3.6 |
OUT1_M | 32 | O | Negative output for channel 1 |
OUT1_P | 27,28 | O | Positive output for channel 1 |
OUT2_M | 39,40 | O | Negative output for channel 2 |
OUT2_P | 35 | O | Positive output for channel 2 |
PVDD | 29,30,31,36,37,38 | P | PVDD supply. Refer to: Section 10.2.1.2.2 and Section 10.3.1.3 |
RESET | 13 | I | Device reset input; active low. Refer to: Section 9.4.5.7, Section 9.4.1, Section 9.4.2 |
VDD | 22 | P | Input power supply. Refer to: Section 10.3.1.1 |
PowerPad™ | P | Ground, connect to grounded heatsink. Placed on top side of device. |
MODE PINS(2) | INPUT MODE(1) | OUTPUT CONFIGURATION | DESCRIPTION | ||||
---|---|---|---|---|---|---|---|
IN2_M | IN2_P | ||||||
X | X | 1N/2N + 1 | 2 × BTL | Stereo, BTL output configuration, AD mode modulation | |||
0 | 0 | 1N/2N + 1 | 1 x PBTL | Mono, Paralleled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation | |||
1 | 1 | 1N/2N + 1 | 1 x BTL | Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode modulation |
最小値 | 最大値 | 単位 | ||
---|---|---|---|---|
電源電圧 | PVDD から GND | –0.3 | 50 | V |
PVDD から GND (過渡現象 8ns 未満)(2) | -0.3 | 57 | V | |
BST_X から GVDD | –0.3 | 50 | V | |
VDD から GND | –0.3 | 50 | V | |
GVDD から GND(2) | -0.3 | 5.5 | V | |
AVDD から GND | -0.3 | 5.5 | V | |
出力ピン | OUT1_M、OUT1_P、OUT2_M、OUT2_P から GND | –0.3 | 50 | V |
OUT1_M、OUT1_P、OUT2_M、OUT2_P から GND (過渡現象 8ns 未満)(2) | -0.3 | 57 | V | |
インターフェイス ピン | IN1_M、IN1_P、IN2_M、IN2_P から GND | -0.3 | 5.5 | V |
FREQ_ADJ、GAIN/CLKSYNC、CMUTE, RESET、OSCP、OSCM から GND | -0.3 | 5.5 | V | |
FAULT、OTW_CLIP から GND | -0.3 | 5.5 | V | |
連続シンク電流、FAULT、OTW_CLIP から GND | 9 | mA | ||
TJ | 動作ジャンクション温度範囲 | 0 | 150 | ℃ |
Tstg | 保管温度範囲 | -40 | 150 | ℃ |