SLOS488F November   2006  – March 2015 TPA6130A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Headphone Amplifiers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Software Shutdown
      3. 8.4.3 Charge Pump Enabled, HP Amplifiers Disabled
      4. 8.4.4 Hi-Z State
      5. 8.4.5 Stereo Headphone Drive
      6. 8.4.6 Dual Mono Headphone Drive
      7. 8.4.7 Bridge-Tied Load Receiver Drive
      8. 8.4.8 Default Mode
      9. 8.4.9 Volume Control
    5. 8.5 Programming
      1. 8.5.1 General I2C Operation
      2. 8.5.2 Single-and Multiple-Byte Transfers
      3. 8.5.3 Single-Byte Write
      4. 8.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 8.5.5 Single-Byte Read
      6. 8.5.6 Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Control Register (Address: 1)
      2. 8.6.2 Volume and Mute Register (Address: 2)
      3. 8.6.3 Output Impedance Register (Address: 3)
      4. 8.6.4 I2C address and Version Register (Address: 4)
      5. 8.6.5 Reserved for test registers (Addresses: 5-8)
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-Blocking Capacitors
        2. 9.2.2.2 Charge Pump Flying Capacitor and CPVSS Capacitor
        3. 9.2.2.3 Decoupling Capacitors
        4. 9.2.2.4 I2C Control Interface Details
          1. 9.2.2.4.1 Addressing the TPA6130A2
        5. 9.2.2.5 Headphone Amplifiers
      3. 9.2.3 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6 Pin Configuration and Functions

YZH (DSBGA) PACKAGE
TPA6130A2 po_YZH_slos488.gif
RTJ (WQFN) PACKAGE
TOP VIEW
TPA6130A2 po_RTJ_slos488.gif

Pin Functions

PIN INPUT/ OUTPUT/ POWER
(I/O/P)		 DESCRIPTION
NAME DSBGA NO. WQFN NO.
VDD A4 20 P Charge pump voltage supply. VDD must be connected to the common VDD voltage supply. Decouple to GND (pin 19 on the QFN) with its own 1 μF capacitor.
GND A3 19 P Charge pump ground. GND must be connected to common supply GND. It is recommended that this pin be decoupled to the VDD of the charge pump pin (pin 20 on the QFN).
CPP A2 18 P Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor to CPP.
CPN A1 17 P Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor to CPN.
LEFTINM B4 1 I Left channel negative differential input. Impedance must be matched to LEFTINP. Connect the left input to LEFTINM when using single-ended inputs.
LEFTINP B3 2 I Left channel positive differential input. Impedance must be matched to LEFTINM. AC ground LEFTINP near signal source while maintaining matched impedance to LEFTINM when using single-ended inputs.
CPVSS B2 15, 16 P Negative supply generated by the charge pump. Decouple to pin 19 on the QFN or a GND plane. Use a 1 μF capacitor.
HPLEFT B1 14 O Headphone left channel output. Connect to left terminal of headphone jack.
RIGHTINM C4 5 I Right channel negative differential input. Impedance must be matched to RIGHTINP. Connect the right input to RIGHTINM when using single-ended inputs.
RIGHTINP C3 4 I Right channel positive differential input. Impedance must be matched to RIGHTINM. AC ground RIGHTINP near signal source while maintaining matched impedance to RIGHTINM when using single-ended inputs.
GND C2 3, 9, 10, 13 P Analog ground. Must be connected to common supply GND. It is recommended that this pin be used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN package.
VDD C1 12 P Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-μF capacitor to analog ground (pin 13 on the QFN).
SD D4 6 I Shutdown. Active low logic. 5V tolerant input.
SDA D3 7 I/O SDA - I2C Data. 5V tolerant input.
SCL D2 8 I SCL - I2C Clock. 5V tolerant input.
HPRIGHT D1 11 O Headphone light channel output. Connect to the right terminal of the headphone jack.
Thermal pad N/A Die Pad P Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is required for mechanical stability and will enhance thermal performance.