JAJSKR7B September   2019  – December 2020 TPA6304-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Bridge-Tied Load (BTL), BD
      2. 6.6.2 Parallel Bridge-Tied Load (PBTL)
      3. 6.6.3 Bridge-Tied Load (BTL), 1SPW
      4. 6.6.4 Bridge-Tied Load (BTL), 384 kHz, BD
      5. 6.6.5 Bridge-Tied Load (BTL), 384 kHz, 1SPW
  7. 7 Parameter measurement information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Single-Ended Analog Inputs
      2. 7.3.2  Gain Control
      3. 7.3.3  Class-D Operation and Spread Spectrum Control
        1. 7.3.3.1 High Frequency Pulse Width Modulator (PWM)
        2. 7.3.3.2 Clock Synchronization
        3. 7.3.3.3 Spread Spectrum Control
      4. 7.3.4  Gate Drive
      5. 7.3.5  Power FETs
      6. 7.3.6  Load Diagnostics
        1. 7.3.6.1 DC Load Diagnostics
          1. 7.3.6.1.1 Automatic DC Load Diagnostics at Device Initialization
          2. 7.3.6.1.2 Automatic DC Load Diagnostics During Hi-Z to MUTE or PLAY Transition
          3. 7.3.6.1.3 Manual Start of DC Load Diagnostics
          4. 7.3.6.1.4 Short-to-Ground
          5. 7.3.6.1.5 Short-to-Power
          6. 7.3.6.1.6 Shorted Load and Open Load
          7. 7.3.6.1.7 Line Output Diagnostics
        2. 7.3.6.2 AC Load Diagnostics
          1. 7.3.6.2.1 Operating Principal
          2. 7.3.6.2.2 Stimulus
          3. 7.3.6.2.3 Load Impedance
          4. 7.3.6.2.4 Tweeter Detection
          5. 7.3.6.2.5 Operation
      7. 7.3.7  Power Supply
        1. 7.3.7.1 Power-Supply Sequence
          1. 7.3.7.1.1 Power-Up Sequence
          2. 7.3.7.1.2 Power-Down Sequence
      8. 7.3.8  Device Initialization and Power-On-Reset (POR)
      9. 7.3.9  Protection and Monitoring
        1. 7.3.9.1 Over Current Protection
        2. 7.3.9.2 DC Detect
        3. 7.3.9.3 Load Current Limit
        4. 7.3.9.4 Clip Detect
        5. 7.3.9.5 Temperature Protection and Monitoring
          1. 7.3.9.5.1 Over Temperature Shutdown (OTSD)
          2. 7.3.9.5.2 Over Temperature Warning (OTW)
          3. 7.3.9.5.3 Thermal Gain Foldback (TGFB)
        6. 7.3.9.6 Power Failures
        7. 7.3.9.7 Load Dump Protection
      10. 7.3.10 Hardware Control Pins
        1. 7.3.10.1 FAULT Pin
        2. 7.3.10.2 STANDBY Pin
        3. 7.3.10.3 GPIO Pins
        4. 7.3.10.4 WARNING
        5. 7.3.10.5 MUTE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal Reporting Signals
        1. 7.4.1.1 Fault Signal
        2. 7.4.1.2 Warning Signal
        3. 7.4.1.3 Clip Detect Signal
      2. 7.4.2 Device States and Flags
        1. 7.4.2.1 Audio Channel States
          1. 7.4.2.1.1 PROTECTIVE SHUTDOWN with AUTO RECOVERY State
          2. 7.4.2.1.2 PROTECTIVE SHUTDOWN State
            1. 7.4.2.1.2.1 Clear Fault
        2. 7.4.2.2 Status and Memory Registers
          1. 7.4.2.2.1 Status Registers
          2. 7.4.2.2.2 Memory Registers
      3. 7.4.3 Fault Events
        1. 7.4.3.1 Overview
        2. 7.4.3.2 Power Fault Events
          1. 7.4.3.2.1 DVDD POR
          2. 7.4.3.2.2 VBAT Over Voltage Fault
          3. 7.4.3.2.3 VBAT Under Voltage Fault
          4. 7.4.3.2.4 PVDD Over Voltage Fault
          5. 7.4.3.2.5 PVDD Under Voltage Fault
          6. 7.4.3.2.6 GVDD Fault
        3. 7.4.3.3 Over Temperature Shut Down (OTSD) Event
        4. 7.4.3.4 Over Current Shut Down (OCSD) Event
        5. 7.4.3.5 DC Fault Event
        6. 7.4.3.6 Load Current Fault Event
        7. 7.4.3.7 Invalid Clock Fault Event
      4. 7.4.4 Warning Events
        1. 7.4.4.1 Overview
        2. 7.4.4.2 Over Temperature Warning Event
        3. 7.4.4.3 Thermal Gain Foldback Warning Event
        4. 7.4.4.4 Load Current Warning Event
        5. 7.4.4.5 Clip Warning Event
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Communication Bus
        1. 7.5.1.1 I2C Address Selection
      2. 7.5.2 I2C Bus Protocol
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 AM Radio Avoidance
      2. 8.1.2 Parallel BTL Operation (PBTL)
      3. 8.1.3 Reconstruction Filter Design
      4. 8.1.4 Bootstrap Capacitors
      5. 8.1.5 Line Driver Applications
    2. 8.2 Typical Applications
      1. 8.2.1 BTL Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Hardware Design Procedure
      2. 8.2.2 PBTL Application
        1. 8.2.2.1 Detailed Hardware Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Electrical Connection of Thermal Pad and Heat Sink
      2. 10.1.2 General Considerations
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒout = 1 kHz, Fsw = 2.1 MHz, Gain = 22 dB, BD Mode, AES17 Filter, LC reconstruction filter: 3.3μH - ASWPA4035S3R3MT in 4Ω, ASWPA6055S3R3MT in 2Ω configuration and 1μF, default I2C settings, see application diagrams in Typical Applications section.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle current All channels playing, no audio input 60 70 mA
IVBAT_IDLE VBAT idle current All channels playing, no audio input 115 130 mA
IDVDD DVDD supply current All channels playing, -60 dB Signal 4 4.5 mA
IPVDD_STBY PVDD standby current STANDBY active, DVDD = 0 V 1.5 10 µA
IVBAT_STBY VBAT standby current STANDBY active, DVDD = 0 V 1 2 µA
OUTPUT POWER
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22 W
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 25 27 W
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C, Inductor DCR = 25mΩ 27 W
PO_BTL Output power per channel, BTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 32 37 W
PO_BTL Output power per channel, BTL 2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 40 45 W
PO_BTL_SQ Output power per channel with square wave, BTL 4 Ω, PVDD = 14.4 V, 2 VRMS Input Square Wave 45 W
PO_BTL_SQ Output power per channel with square wave, BTL 4 Ω, PVDD = 16 V, 2 VRMS Input Square Wave 55 W
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 38 43 W
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 47 53 W
EFFP Power efficiency 4 channels operating, 25 W output power per channel, RL = 4 Ω, PVDD = 14.4 V, TC = 25°C; (includes device and LC filter losses) 88 %
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistance 25°C, Including bond wire and package resistance 100 mΩ
RDS(on) FET drain-to-source resistance 25°C, Not including bond wire and package resistance 80 mΩ
AUDIO PERFORMANCE
Vn Output noise voltage Zero input, A-weighting, 10 dB gain 35 µV
Vn Output noise voltage Zero input, A-weighting, 16 dB gain 42 µV
Vn Output noise voltage Zero input, A-weighting, 22 dB gain 60 µV
Vn Output noise voltage Zero input, A-weighting, 28 dB gain 75 µV
THD+N Total harmonic distortion + noise 0.013 %
G Gain Level 1 9 10 10.5 dB
G Gain Level 2 15 16 16.5 dB
G Gain Level 3 21 22 22.5 dB
G Gain Level 4 27 28 28.5 dB
GCH Channel-to-channel gain variation –0.5 0 0.5 dB
Crosstalk Channel crosstalk –90 dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 80 dB
GMUTE Output attenuation Assert MUTE and compare to amp playing 1W audio into 4 Ω 100 117 dB
VCLICK Click and Pop Zero input, ITU-filter, 28dB gain 7 mV
Vn_LINEOUT Line output noise voltage Zero input, A-weighting, channel set to Line Output, RL = 600 Ω, Gain = 16 dB 42 µV
THD+N Line output Total harmonic distortion + noise VOUT = 2 VRMS , channel set to Line Output 0.01 %
ANALOG INPUT PINS
RIN Input impedance IN_1, IN_2, IN_3, IN_4 80 kΩ
RIN Input impedance IN_REF 20 kΩ
VIN Maximum input voltage swing VIN AC coupled through capacitor. Pins IN_1, IN_2, IN_3, IN_4 1 VRMS
VIN Maximum input voltage swing IN_REF 5 mV
IIN Maximum input current IN_1, IN_2, IN_3, IN_4, IN_REF 10 mA
DIGITAL INPUT PINS
VIH Input logic level high 70 %DVDD
VIL Input logic level low 30 %DVDD
IIH Input logic current VI = DVDD 33 50 µA
IIL Input logic current VI = 0 –50 –33 µA
DIGITAL OUTPUT PINS
VOH Output voltage for logic level high I = ±2 mA 90 %DVDD
VOL Output voltage for logic level low I = ±2 mA 10 %DVDD
BYPASS VOLTAGES
VGVDD Gate drive bypass pin voltage 5 V
VAVDD Analog bypass pin voltage 5 V
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV_SET PVDD overvoltage shutdown set 18.5 20 22 V
VPVDD_OV_HYS PVDD overvoltage recovery hysteresis 0.5 V
VVBAT_OV_SET VBAT overvoltage shutdown set 18.5 20 22 V
VVBAT_OV_HYS VBAT overvoltage recovery hysteresis 0.5 V
UNDERVOLTAGE (UV) PROTECTION
VBATUV_SET VBAT undervoltage shutdown set 3.7 4.5 V
VBATUV_HYS VBAT undervoltage recovery hysteresis 0.3 V
PVDDUV_SET PVDD undervoltage shutdown set 3.7 4.5 V
PVDDUV_HYS PVDD undervoltage recovery hysteresis 0.3 V
POWER-ON RESET (POR)
VPOR_SET DVDD power on reset set Increasing DVDD 1.9 V
VPOR_HYS DVDD power on reset recovery hysteresis 0.5 V
VPOR_OFF DVDD power off threshold Decreasing DVDD 1.5 2.4 V
OVERTEMPERATURE (OT) PROTECTION
OTW(i) Per channel over-temperature warning 160 °C
OTSD(i) Per channel over-temperature shutdown 175 °C
OTW Global junction over-temperature warning Default value (see Misc Control Register 1) 130 °C
OTSD Global junction over-temperature shutdown 160 °C
OTHYS Over-temperature recovery hysterisis 15 °C
LOAD OVERCURRENT PROTECTION
ILIMIT Load Overcurrent limit OC level 1, load current (default) 3.0 3.4 A
ILIMIT Load Overcurrent limit OC level 2, load current 3.5 4 A
ILIMIT Load Overcurrent limit OC level 3, load current 5.0 5.8 A
ILIMIT Load Overcurrent limit OC level 4, load current 6.0 6.5 A
ISD Overcurrent shutdown OC level 1, any short to supply, ground, or other channels (default) 4.7 6 A
ISD Overcurrent shutdown OC level 2, any short to supply, ground, or other channels 5.5 7 A
ISD Overcurrent shutdown OC level 3, any short to supply, ground, or other channels 8.0 10 A
ISD Overcurrent shutdown OC level 4, any short to supply, ground, or other channels 9.0 11 A
DC DETECT
DCFAULT Output DC fault protection 1 1.75 2.5 V
SYNC
fsync Supported SYNC frequency, master mode Misc Control 2 Register, PWM_FREQUENCY: 00, fsw = 2.1MHz 8.4 MHz
fsync Supported SYNC frequency, master mode Misc Control 2 Register, PWM_FREQUENCY: 01, fsw = 2.3MHz 9.2 MHz
Δfsync SYNC frequency deviation from nominal, master mode –10 10 %
fsync Supported SYNC frequency, slave mode fsw = 2.1MHz 8.4 MHz
fsync Supported SYNC frequency, slave mode fsw = 2.3 MHz 9.2 MHz
Δfsync Supported SYNC frequency deviation, slave mode –10 10 %
Dsync Supported SYNC duty cycle, slave mode 44 50 56 %
LOAD DIAGNOSTICS
S2P Maximum resistance to detect a short from OUT pin(s) to PVDD 8000 Ω
S2G Maximum resistance to detect a short from OUT pin(s) to ground 300 Ω
SL Shorted load detection tolerance One channel, other channels in Hi-Z ±12.5%
OL Minimum impedance detected as open load Other channels in Hi-Z 110 Ω
TDC_DIAG DC diagnostic time 4 channels, no faults 174 ms
LO Maximum detectable impedance for line output mode 12 kΩ
TLINE_DIAG Line output diagnostic time 150 ms
ACIMP AC impedance accuracy ƒ = 18.5 kHz, RL = 4 Ω, Impedance at output pins ±0.75 Ω
TAC_DIAG AC diagnostic time 4 channels, ƒ = 18.5 kHz 217 ms
FAC AC diagnostic test frequency Default frequency 18.5 kHz
I2C CONTROL PORT
tBUS Bus free time between start and stop conditions 1.3 µs
tH1 Hold Time, SCL to SDA 0 ns
tH2 Hold Time, start condition to SCL 0.6 µs
tSTART I2C Startup Time After DVDD Power On Reset 10 ms
tRISE (1) Rise Time, SCL and SDA 300 ns
tFALL (1) Fall Time, SCL and SDA 300 ns
tSU1 Setup, SDA to SCL 100 ns
tSU2 Setup, SCL to Start Condition 0.6 µs
tSU3 Setup, SCL to Stop Condition 0.6 µs
tW(H) Required Pulse Duration SCL High 0.6 µs
tW(L) Required Pulse Duration SCL Low 1.3 µs
(1) Specified by design.