SLVSDG3C March   2016  – December 2016 TPD1E01B04

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  IEC 61000-4-2 ESD Protection
      2. 7.3.2  IEC 61000-4-4 EFT Protection
      3. 7.3.3  IEC 61000-4-5 Surge Protection
      4. 7.3.4  IO Capacitance
      5. 7.3.5  DC Breakdown Voltage
      6. 7.3.6  Ultra Low Leakage Current
      7. 7.3.7  Low ESD Clamping Voltage
      8. 7.3.8  Supports High Speed Interfaces
      9. 7.3.9  Industrial Temperature Range
      10. 7.3.10 Easy Flow-Through Routing Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPD1E01B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.

8.2 Typical Application

TPD1E01B04 app_diagram.gif Figure 14. USB Type-C for Thunderbolt 3 ESD Schematic

8.2.1 Design Requirements

For this design example eight TPD1E01B04DPL devices and two TPD4E05U06 devices are being used in a USB Type-C for Thunderbolt 3 application. This provides a complete ESD protection scheme.

Given the Thunderbolt 3 application, the parameters listed in Table 1 are known.

Table 1. Design Parameters

DESIGN PARAMETER VALUE
Signal range on superspeed Lines 0 V to 3.6 V
Operating frequency on superspeed Lines up to 10 GHz
Signal range on CC, SBU, and DP/DM Lines 0 V to 5 V
Operating frequency on CC, SBU, and DP/DM Lines up to 480 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Signal Range

The TPD1E01B04 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed pairs on the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports the CC, SBU, and DP-DM lines.

8.2.2.2 Operating Frequency

The TPD1E01B04DPL has a 0.18 pF (typical) capacitance, which supports the Thunderbolt 3 data rates of 20 Gbps. The TPD4E05U06 has a 0.5-pF (typical) capacitance, which easily supports the CC, SBU, and DP-DM data rates.

8.2.3 Application Curves

TPD1E01B04 USB3.1_Eye_Unpopulated.png
Figure 15. USB 3.1 Gen 2 10-Gbps Eye Diagram
(Bare Board)
TPD1E01B04 D010_SLVSDG3.gif
Figure 17. Insertion Loss
TPD1E01B04 USB3.1_Eye_Populated_TPD1E01B04.png
Figure 16. USB 3.1 Gen 2 10-Gbps Eye Diagram
(with TPD1E01B04DPL)