SLLSEB2E February   2012  – October 2015 TPD1E6B06

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VRWM Maximum voltage allowed from pin 1 to pin 2, or pin 2 to pin 1 –5 5 V
IPP Peak pulse current (tp = 8/20 μs) 3.8 A
PPP Peak pulse power (tp = 8/20 μs) 50 W
TA Operating temperature –40 125 °C
Tstg Storage temperature –65 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
IEC 61000-4-2 contact discharge ±15000
IEC 61000-4-2 air-gap discharge ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2500 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating free-air temperature, TA –40 125 °C
Operating Voltage Pin 1 to 2 or Pin 2 to 1 –5 5 V

6.4 Thermal Information

THERMAL METRIC(1) TPD1E6B06 UNIT
DPL (X2SON)
2 PINS
RθJA Junction-to-ambient thermal resistance 567.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 253.2 °C/W
RθJB Junction-to-board thermal resistance 31.6 °C/W
ψJT Junction-to-top characterization parameter 379.1 °C/W
ψJB Junction-to-board characterization parameter 31.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage ILEAK = 100 nA ±5 V
ILEAK Leakage current Pin 1 = 5 V, Pin 2 = 0 V 100 nA
VClamp1,2 Clamp voltage with ESD strike on pin 1, pin 2 grounded. IPP = 1 A, tp = 8/20 μs 10 V
IPP = 5 A, tp = 8/20 μs 14
VClamp2,1 Clamp voltage with ESD strike on pin 2, pin 1 grounded. IPP = 1 A, tp = 8/20 μs 10 V
IPP = 5 A, tp = 8/20 μs 14
RDYN Dynamic resistance Pin 1 to Pin 2(1) 0.55 Ω
Pin 2 to Pin 1(1) 0.55
CIO I/O capacitance VIO = 2.5 V; ƒ = 1 MHz 6 pF
VBR1,2 Breakdown voltage, pin 1 to pin 2 IIO = 1 mA 6 V
VBR2,1 Breakdown voltage, pin 2 to pin 1 IIO = 1 mA 6 V
(1) Extraction of RDYN using least squares fit of TLP characteristics between IPP = 10 A and IPP = 20 A.

6.6 Typical Characteristics

TPD1E6B06 D001_TPD1E6B06_Graphs.gif Figure 1. ESD Clamp Voltage +8-kV Contact ESD
TPD1E6B06 D008_TPD1E6B06_Graphs.gif Figure 3. Clamping Voltage VTLP = F(ITLP), PIN1 to PIN2
TPD1E6B06 D003_TPD1E6B06_Graphs.gif Figure 5. IV Curve
TPD1E6B06 D005_TPD1E6B06_Graphs.gif
Figure 7. Surge Graph, Pin 2 to Pin 1
TPD1E6B06 D011_TPD1E6B06_Graphs.gif Figure 9. Insertion Loss, Pin 2 to Pin 1
TPD1E6B06 D002_TPD1E6B06_Graphs.gif Figure 2. ESD Clamp Voltage –8-kV Contact ESD
TPD1E6B06 D009_TPD1E6B06_Graphs.gif Figure 4. Clamping Voltage VTLP = F(ITLP), PIN2 to PIN1
TPD1E6B06 D004_TPD1E6B06_Graphs.gif Figure 6. Surge Graph, Pin 1 to Pin 2
TPD1E6B06 D010_TPD1E6B06_Graphs.gif Figure 8. Insertion Loss, Pin 1 to Pin 2