SLLSEH9B October   2013  – July 2016 TPD1S414

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (EN, ACK Pins)
    6. 6.6  Electrical Characteristics (OVP Circuit)
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics (nFET)
    9. 6.9  Supply Current Consumption
    10. 6.10 Thermal Shutdown Feature
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overvoltage Protection on VBUS_CON up to 30-V DC
      2. 7.3.2 Low RON nFET Switch Supports Host and Charging Mode
      3. 7.3.3 ±15-kV IEC 61000-4-2 Level 4 ESD Protection
      4. 7.3.4 100-V IEC 61000-4-5 µs Surge Protection
      5. 7.3.5 Start-Up and OVP Recovery Delay
      6. 7.3.6 Integrated Input Enable and Status Output Signal
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 VBUS_CON < VUVLO
      2. 7.4.2 VUVLO < VBUS_CON < VOVP
      3. 7.4.3 VBUS_CON > VOVP
      4. 7.4.4 OVP Operation
      5. 7.4.5 Host/OTG Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB VBUS Voltage Range
        2. 8.2.2.2 USB VBUS Operating Current
        3. 8.2.2.3 VBUS_CON and VBUS_SYS Capacitance
        4. 8.2.2.4 IEC 61000-4-5 100-V Open-Circuit Surge
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YZ|12
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

TPD1S414 can be routed in a single-layer PCB. PCB traces to VBUS_SYS, VBUS_CON, and GND can be routed in the fashion shown in Figure 12.

Shorting all of the VBUS_SYS pins together, all the VBUS_CON pins together, and all the GND pins together helps provide the lowest resistance between the USB connector and the PMIC. For this example, the trace widths to VBUS_SYS, VBUS_CON are 25 mils (0.635 mm) under TPD1S414. There are no VIAs required within the SMD pads in this design. Stitching VIAs for GND can be placed near the component instead.

The decoupling capacitors per the Recommended Operating Conditions must be placed as close as possible to the TPD1S414. There must be a short path from the device ground pins to the system ground plane. This ensures best protection under ESD and surge transients.

10.2 Layout Example

TPD1S414 layout_sllseh9.gif Figure 12. TPD1S414 Layout Example