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  • TPD2E007 2-Channel ESD Protection Array for AC-Coupled/Negative-Rail Data Interfaces

    • SLVS796I September   2008  – March 2016 TPD2E007

      PRODUCTION DATA.  

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  • TPD2E007 2-Channel ESD Protection Array for AC-Coupled/Negative-Rail Data Interfaces
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge Protection
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 Level 4 ESD Protection
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 Low 50-nA Leakage Current
      5. 7.3.5 Space-Saving PicoStar and SOT Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on IO1 and IO2 Pins
        2. 8.2.2.2 Surge Withstand
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

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DATA SHEET

TPD2E007 2-Channel ESD Protection Array for AC-Coupled/Negative-Rail Data Interfaces

1 Features

  • IEC 61000-4-2 Level 4 ESD Protection
    • ±8-kV IEC 61000-4-2 Contact Discharge
    • ±15-kV IEC 61000-4-2 Air-Gap Discharge
  • IEC 61000-4-5 Surge Protection
    • 4.5-A Peak Pulse Current (8/20-µs Pulse)
  • IO Capacitance 15 pF (Max)
  • Low 50-nA Leakage Current
  • Space-Saving PicoStar™ and SOT Package

2 Applications

  • Cell Phones
  • Audio Interface Connections
  • Consumer Electronics (DVR, Set-Top Box, TV)
  • Industrial Interfaces (RS-232, RS-485, RS-422, LVDS)

3 Description

This device is a transient voltage suppressor (TVS) based electrostatic discharge (ESD) protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, and so forth) without compromising signal integrity. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector.

The TPD2E007 is offered in a 4-bump PicoStar and 3-pin SOT (DGK) packages. The PicoStar package (YFM), with only 0.15 mm (Max) package height, is recommended for ultra space saving application where the package height is a key concern. The PicoStar package can be used in either embedded PCB board applications or in surface mount applications. The industry standard SOT package offers straightforward board layout option in legacy designs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPD2E007 SOT (3) 2.00 mm x 1.25 mm
PicoStar (4) 0.77 mm x 0.77 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Example Schematic

TPD2E007 RS232-Surge-Diagram.gif

Equivalent Schematic Representation

TPD2E007 lbd_lvs796.gif

4 Revision History

Changes from H Revision (January 2016) to I Revision

  • Made changes to ESDS section Go

Changes from G Revision (December 2015) to H Revision

  • Updated the break-down voltage for clarity Go

Changes from F Revision (August 2014) to G Revision

  • Updated the Handling Ratings table to an ESD Ratings table and moved Tstg to the Absolute Maximum Ratings table Go
  • Added ƒ = 10 MHz to the Channel input capacitance test condition in the Electrical Characteristics table Go
  • Added Community Resources Go

Changes from E Revision (August 2010) to F Revision

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from D Revision (October 2009) to E Revision

  • Added max continuous power dissipation value for DCK packageGo

5 Pin Configuration and Functions

DCK Package
3-Pin SOT
Top View
TPD2E007 po_dck_lvs796.gif


YFM Package
4-Pin PicoStar
Bottom View
TPD2E007 po_lvs796.gif
0.8 mm × 0.8 mm (0.4 mm pitch)

Pin Functions

PIN I/O DESCRIPTION
NAME DCK
NO.		 YFM
NO.
GND 3 B1, B2 G Ground
IO1 1 A1 IO ESD protected channel
IO2 2 A2 IO ESD protected channel

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIO –13.5 13.5 V
Continuous power dissipation
(TA = 70°C)		 YFM package 270 mW
DCK package 218
Operating temperature –40 85 °C
TJ Junction temperature 150 °C
Bump temperature (soldering) Infrared (15 s) 220 °C
Vapor phase (60 s) 215
Lead temperature (soldering, 10 s) 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±15000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: Surge Protection

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 ESD ratings Contact ±8000 V
Air gap ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIO Operating voltage –13 13 V
Operating temperature –40 85 °C

6.5 Thermal Information

THERMAL METRIC(1) TPD2E007 UNIT
DCK (SOT) YFM (PicoStar)
3 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 251.9 175.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 115.4 39.2 °C/W
RθJB Junction-to-board thermal resistance 42.4 28.7 °C/W
ψJT Junction-to-top characterization parameter 9.4 8.3 °C/W
ψJB Junction-to-board characterization parameter 42.2 28.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VBRF Break-down voltage, pin 1 or 2 to GND IIO = 10 mA 14 V
VBRR Break-down voltage, GND to pin 1 or 2 IIO = 10 mA 14 V
IIO Channel leakage current 20 50 nA
Rd Dynamic resistance 3.5 Ω
CIN Channel input capacitance VIO = 2.5 V; ƒ = 10 MHz 10 15 pF
(1) Typical values are at VCC = 5 V and TA = 25°C.

6.7 Typical Characteristics

IEC Clamping Waveforms (20 ns/div)
TPD2E007 iecclamp_pos8_lvs796.gif Figure 1. 8-kV Contact
TPD2E007 cap_involt_lvs796.gif Figure 3. Capacitance vs Input Voltage at TA = 27°C
TPD2E007 iecclamp_neg8_lvs796.gif Figure 2. –8-kV Contact
TPD2E007 diodebrkdn_lvs796.gif Figure 4. Diode Breakdown Voltage Data at TA = 27°C

 
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