SLLS683F JULY   2006  – October 2015 TPD3E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRS|6
  • DRL|5
  • DRY|6
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The TPD3E001 is a three-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. The TPD3E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device has a 1.5-pF IO capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra low leakage current (< 1 nA maximum) is suitable for precision analog measurements in applications like glucose meters and heart rate monitors. The wide voltage range on VCC (up to 5.5V) gives this device the flexibility to be used in a wide variety applications. Having 3-channels of ESD protection makes this device particularly well suited to protect a micro-AB USB connector, which has three signal lines to be protected (D+, D-, ID). The VBUS pin can also be protected by connecting it to VCC on TPD3E001. Therefore, TPD3E001 is a one-chip solution to provide Level 4 IEC 61000-4-2 ESD protection on every pin of the micro-AB USB connector.

7.2 Functional Block Diagram

TPD3E001 lb_lls683.gif

7.3 Feature Description

TPD3E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD3E001's low loading capacitance makes it ideal for protection high-speed signal terminals.

7.4 Device Functional Modes

TPD3E001 is a passive-integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD3E001 (usually within 10's of nano-seconds) the device reverts back to a high-impedance state.