SLVSAM5A January   2011  – April 2016 TPD3F303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6  Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - Surge Protection
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional EMI Filtering and Line Termination With Integrated ESD Protection
      2. 7.3.2 IEC 61000-4-2 ESD Protection
      3. 7.3.3 DC Breakdown Voltage
      4. 7.3.4 Low Leakage Current
      5. 7.3.5 Low Noise C-R-C Filter Topology
      6. 7.3.6 Integrated VCC Clamp
      7. 7.3.7 Space-Saving Packages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Required ESD Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DQD or DPV Package
8-Pin WSON or USON
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
CLK_OUT 2 Output Clock Input and Output signals.
CLK_IN 7 Input
DATA1_IN 8 Input Data and Rest signals Input, Output pins. The DATA1 and DATA2 are symmetric circuits. They can be used interchangeably for either DATA or RESET pins based off board layout scheme.
DATA2_IN 6
DATA1_OUT 1 Output
DATA2_OUT 3
GND GND Ground Ground connection for the EMI filter. It is very important to connect the device GND to the printed circuit board ground plane through Vias directly under the package.
NC 4 No Connect Not connected to any internal circuit. Leave this pin floating.
VCC 5 Power Clamp ESD Clamp circuit for the VCC pin.