JAJSJE7C March   2016  – August 2020 TPD3S014-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics: TJ = TA = 25°C
    8. 6.8 Electrical Characteristics: –40°C ≤ TA ≤ 105°C
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1.     18
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 Output Discharge
      6. 8.3.6 Input and Output Capacitance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
      3. 8.4.3 Operation of Level 4 IEC 61000-4-2 ESD Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Implementing Active Low Logic
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Application Information

The TPD3S014-Q1 is a device that features a current limited load switch and a two-channel TVS based ESD protection diode array. It is typically used to provide a complete protection solution for USB host ports. USB host ports are required by the USB specification to provide a current limit on the VBUS path in order to protect the system from overcurrent conditions on the port that could lead to system damage and user injury. Additionally, USB ports typically require system level IEC ESD protection because of direct end-user interaction. The following design procedure can be used to determine how to properly implement the TPD3S014-Q1 in your systems to provide a complete, one-chip solution for your USB ports.