JAJSJ53B may   2020  – april 2023 TPD3S713-Q1 , TPD3S713A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FAULT Response
      2. 8.3.2 Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3 DP and DM Protection
      4. 8.3.4 VBUS OVP Protection
      5. 8.3.5 Output and DP or DM Discharge
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Thermal Sensing
      9. 8.3.9 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 Client Mode
      3. 8.4.3 High-Bandwidth Data-Line Switch
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 5.5 V, V(EN) = V(INT1) = V(ILIM_SEL) = V(IN), V(INT2) = GND, R(FAULT) = 10 kΩ, R(IMON) = 2.55 kΩ, R(ILIM_HI) = 52.3 kΩ. Positive currents are into pins. Typical values are at TJ = 25°C. All voltages are with respect to GND.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OUT – POWER SWITCH
rDS(on)On-resistance(1)TJ = 25°C7390mΩ
–40°C ≤TJ ≤ 125°C73120
IlkgReverse leakage currentVBUS = 5 V, VIN = VEN = 0 V, –40°C ≤ TJ ≤ 125°C, measure I(IN)0.012µA
OUT – DISCHARGE
R(DCHG)Discharge resistance (ILIM_SEL change)400500630Ω
ENABLE, ILIM_SEL, INT1, INT2 INPUTS
Input pin rising logic threshold voltage0.81.352V
Input pin falling logic threshold voltage0.71.151.65V
Hysteresis(2)200mV
Input currentPin voltage = 0 V or 5.5 V–11µA
CURRENT LIMIT
IOSVBUS short-circuit current limitRILIM_HI or RILIM_LO = 80.6 kΩ385571mA
RILIM_HI or RILIM_LO = 52.3 kΩ6282102
RILIM_HI or RILIM_LO = 22.1 kΩ166192218
RILIM_HI or RILIM_LO = 15.4 kΩ245275305
RILIM_HI or RILIM_LO = 6.98 kΩ560600640
RILIM_HI Shorted to GND86011501440
RILIM_HI Shorted to GND
I(IN_OFF)Disabled IN supply currentV(EN) = 0 V, V(BUS) = 0 V, –40°C ≤ TJ ≤ 125°C, no 5.1-kΩ resistor (open) between BIAS and VBUS0.110µA
I(IN_ON)Enabled IN supply currentV(INT1) = V(ILIM_SEL) = High200280µA
UNDERVOLTAGE LOCKOUT, IN
V(UVLO)UVLO threshold voltageIN rising3.94.14.3V
IN falling3.33.53.7
FAULT
Output low voltageI(FAULT) = 1 mA100mV
Off-state leakageV(FAULT) = 5.5 V2µA
THERMAL SHUTDOWN
T(OTSD2)Thermal shutdown threshold155°C
T(OTSD1)Thermal shutdown threshold in current-limit135°C
Hysteresis(3)20°C
DM_IN AND DP_IN OVERVOLTAGE PROTECTION
V(OV_Data)Protection trip thresholdDP_IN and DM_IN rising3.33.94.15V
Hysteresis(3)100mV
R(DCHG_Data)Discharge resistor after OVP(3)DP_IN = DM_IN = 18 V, IN = 5 V or 0 V200kΩ
DP_IN = DM_IN = 5 V, IN = 5 V370
DP_IN = DM_IN = 5 V, IN = 0390
BUS OVERVOLTAGE PROTECTION
V(OV_BUS)Protection trip thresholdVBUS rising5.6566.35V
Hysteresis(3)90mV
R(DCHG_BUS)Discharge resistorVBUS = 18 V, IN = 5 V5585kΩ
VBUS = 18 V, IN = 080120
CABLE COMPENSATION
I(CS)Sink currentLoad = 0.5 A, 2.5 V ≤ V(CS) ≤ 5.5 V190210230µA
CURRENT MONITOR OUTPUT (IMON)
I(IMON)Source currentLoad = 0.5 A, 0 ≤ V(IMON) ≤ 2.5 V245265285µA
HIGH-BANDWIDTH ANALOG SWITCH
R(HS_ON)DP and DM switch on-resistanceV(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30 mA3.26.5Ω
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) = –15 mA3.87.6
|ΔR(HS_ON)|Switch resistance mismatch between DP and DM channelsV(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30 mA0.050.15Ω
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) = –15 mA0.050.15
C(IO_OFF)DP and DM switch off-state capacitance(4)VEN = 0 V, V(DP_IN) = V(DM_IN) = 0.3 V, Vac = 0.03 VPP, f = 1 MHz8.8pF
C(IO_ON)DP and DM switch on-state capacitance(4)V(DP_IN) = V(DM_IN) = 0.3 V, Vac = 0.03 VPP, f = 1 MHz10.9pF
Off-state isolation(4)V(EN) = 0 V, f = 250 MHz12dB
On-state cross-channel isolation(4)f = 250 MHz34dB
Ilkg(OFF)Off-state leakage currentVEN = 0 V, V(DP_IN) = V(DM_IN) = 3.6 V, V(DP_OUT) = V(DM_OUT) = 0 V, measure I(DP_OUT) and I(DM_OUT)0.11.5µA
BWBandwidth (–3 dB)(4)R(L) = 50 Ω1230MHz
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.
(2) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.
(3) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.
(4) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.