JAJSJN8C January   2016  – August 2020 TPD3S714-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  AEC-Q100 Qualified
      2. 8.3.2  Short-to-Battery and Short-to-Ground Protection on VBUS_CON
      3. 8.3.3  Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
      4. 8.3.4  ESD Protection on VBUS_CON, VD+, VD–
      5. 8.3.5  Low RON nFET VBUS Switch
      6. 8.3.6  High Speed Data Switches
      7. 8.3.7  Hiccup Current Limit
      8. 8.3.8  Fast Overvoltage Response Time
      9. 8.3.9  Integrated Input Enable
      10. 8.3.10 Fault Output Signal
      11. 8.3.11 Thermal Shutdown Feature
      12. 8.3.12 16-pin SSOP Package
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Overvoltage Condition
      3. 8.4.3 Overcurrent Condition
      4. 8.4.4 Short-Circuit Condition
      5. 8.4.5 Device Logic Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Short-to-Battery Tolerance
        2. 9.2.2.2 Maximum Current on VBUS
        3. 9.2.2.3 USB Data Rate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VBUS Path
    2. 10.2 VIN Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON = float (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT CONSUMPTION
IVBUS_SLEEPVBUS sleep current consumptionMeasured at VBUS_SYS pin, EN = 5 V45150µA
IVBUSVBUS operating current consumptionMeasured at VBUS_SYS pin285380µA
IVINLeakage current for VINMeasured at VIN pin, VIN = 3.6 V1225µA
ION(LEAK)Leakage through VBUS while shorted to battery and powered onMeasured flowing in to VBUS_SYS pin, VBUS_SYS = 5 V, VBUS_CON = 18 V120µA
IOFF(LEAK)Leakage through VBUS while shorted to battery and unpoweredMeasured flowing out of VBUS_SYS pin, VBUS_SYS = 0 V, VBUS_CON = 18 V50µA
IVD(OFF_LEAK)Leakage into data path while shorted to battery and unpoweredMeasured flowing in to VD+ or VD– pins, VBUS_SYS = 0 V, VD+ or VD– = 18 V, VIN = 0 V, D+/D– = 0 V80µA
IVD(ON_LEAK)Leakage into data path while shorted to battery and powered onMeasured flowing in to VD+ or VD– pins, VBUS_SYS = 5 V, VD+ or VD– = 18 V, D+/D– = 0 V80µA
VIN PIN
VUVLO(RISING)Undervoltage lockout rising for VINVINRamp VIN down until FLT is deasserted, EN = 5 V2.62.72.9V
VUVLO(FALLING)Undervoltage lockout falling for VINRamp VIN until FLT is asserted, EN = 5 V2.52.62.8
EN, FLT PINS
VIHHigh-level input voltageENSet EN = 0 V; Sweep EN to 1.4 V; Measure when FLT is asserted1.2V
VILLow-level input voltageENSet EN = 3.3 V; Sweep EN from 3.3 V to 0.5 V; Measure when FLT is deasserted0.8V
IILInput leakage currentENV(EN) = 3.3 V ; Measure Current into EN pin1µA
VOLLow-level output voltageFLTIOL = 3 mA0.4V
OCP CIRCUIT—VBUS
ILIMOvercurrent limitVBUSProgressively load VBUS_CON until device asserts FLT550700850mA
OVERTEMPERATURE PROTECTION
TSD(RISING)The rising overtemperature protection shutdown thresholdVBUS_SYS = 5 V, EN = 0 V, No Load on VBUS_CON, TA stepped up until FLT is asserted150165180℃
TSD(FALLING)The falling overtemperature protection shutdown thresholdVBUS_SYS = 5 V, EN = 0 V, No Load on VBUS_CON, TA stepped down from TSD(RISING) until FLT is deasserted125130140℃
TSD(HYST)The overtemperature protection shutdown threshold hysteresisTSD(RISING) – TSD(FALLING)103555℃
OVP CIRCUIT—VBUS
VOVP(RISING)Input overvoltage protection thresholdVBUS_CONIncrease VBUS_CON from 5 V to 7 V. Measure when FLT is asserted5.45.65.8V
VHYS(OVP)Hysteresis on OVPVBUS_CONDifference between rising and falling OVP thresholds on VBUS_CON50mV
TOVP(FALLING)Input overvoltage protection thresholdVBUS_CONDecrease VBUS_CON from 7 V to 5 V. Measure when FLT is deasserted5.365.74V
VUVLO(SYS_RISING)Undervoltage lockout rising for VBUS_SYSVBUS_SYSVBUS_SYS voltage rising from 0 V to 5 V3.13.33.6V
VHYS(UVLO_SYS)VBUS_SYS UVLO hysteresisVBUS_SYSDifference between rising and falling UVLO thresholds on VBUS_SYS5075100mV
VUVLO(SYS_FALLING)Undervoltage lockout falling for VBUS_SYSVBUS_SYSVBUS_SYS voltage falling from 7 V to 3 V33.23.5V
VSHRT(RISING)Short-to-ground comparator rising thresholdVBUS_CONIncrease VBUS_CON voltage from 0 V until the device transitions from the short-circuit to over-current mode of operation2.52.62.7V
VSHRT(FALLING)Short-to-ground comparator falling thresholdVBUS_CONSet VBUS_SYS = 5 V; VIN = 3.3 V; EN = 0 V; Decrease VBUS_CON voltage from 5 V until the device transitions from the overcurrent to short-circuit mode of operation2.42.52.6V
VSHRT(HYST)Short-to-ground comparator hysteresisVBUS_CONDifference between VSHRT(RISING) and VSHRT(FALLING)100125150mV
ISHRTShort-to-ground current sourceVBUS_CONCurrent sourced from VBUS_SYS when device is in short-circuit mode150350mA
OVP CIRCUIT—VD+/VD–
VOVP(RISING)Input overvoltage protection thresholdVD+/VD–Increase VD+ or VD– (with D+ and D–) from 3.3 V to 4.5 V. Measure the value at which FLT is assertedVIN + 0.6VIN + 0.8VIN + 1V
VHYS(OVP)Hysteresis on OVPVD+/VD–Difference between rising and falling OVP thresholds on VD+/VD–50mV
VOVP(FALLING)Input overvoltage protection thresholdVD+/VD–Decrease VD+ or VD– (with D+ or D–) from 4.5 V to 2 V. Measure the value at FLT is deassertedVIN + 0.525VIN + 0.75VIN + 0.975V
SHORT-TO-BATTERY
V(VBUS_STB)VBUS hotplug short-to-battery toleranceVBUS_CONCharge battery-equivalent capacitor to test voltage then discharge to pin under test through a 1-meter, 18-gauge wire. (See Figure 7-1 for more details)18V
V(DATA_STB)Data line hotplug short-to-battery toleranceVD+/VD–18V
DATA LINE SWITCHES—VD+ to D+ or VD–to D–
CONEquivalent on capacitanceCapacitance of D+/D– switches when enabled - measure on connector side across bias voltage 0 V to 0.4 V6.2pF
RONOn resistanceMeasure resistance between D+ and VD+ or D– and VD–, voltage between 0 and 0.4 V46.5Ω
RON(Flat)On resistance flatnessMeasure resistance between D+ and VD+ or D– and VD–, sweep voltage between 0 V and 0.4 V0.21Ω
BWONOn bandwidth (–3 dB)Measure S21 bandwidth from D+ to VD+ or D– to VD– with voltage swing = 400 mVpp, VCM= 0.2 V860MHz
BWON_DIFFOn bandwidth (–3 dB)Measure SDD21 bandwidth from D+ to VD+ and D– to VD– with voltage swing = 800 mVpp differential, VCM = 0.2 V1050MHz
XtalkCrosstalkMeasure S21 bandwidth from D+ to VD– or D– to VD+ with voltage swing = 400 mVpp. Be sure to terminate open sides to 50 ohms. f = 480 MHz–34dB
nFET SWITCH—VBus
R(DISCHARGE)Output discharge resistanceEN = 5 V, Set VBUS_CON = 5 V and measure current flow to ground12500Ω
RONSwitch ON resistanceVBUS_CON = 5 V, IOUT = 0.5 A63150mΩ