JAJSRJ3E December   2012  – October 2024 TPD4E1B06

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Ultra Low Leakage Current 0.5 nA (Maximum)
      2. 6.3.2 Transient Protection for 4 I/O Lines
      3. 6.3.3 I/O Capacitance 0.7 pF (Typical)
      4. 6.3.4 Bi-Directional (ESD) Protection Diode Array
      5. 6.3.5 Low ESD Clamping Voltage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Signal Range on IO1, IO2, IO3, and IO4 Pins
        2. 7.2.2.2 Operating Frequency
      3. 7.2.3 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Device Functional Modes

TPD4E1B06 is a passive integrated circuit that activates whenever fast transient voltages above VBR or below –VBR are present on the circuit being protected. During ESD events, voltages as high as ±12 kV can be directed to ground through the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD4E1B06 (usually within 10’s of nano-seconds) the device reverts to passive.