JAJSP20 November   2024 TPD4S480

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—IEC Specification
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63-VDC Tolerant
      2. 6.3.2 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      3. 6.3.3 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      4. 6.3.4 EPR Adapter
        1. 6.3.4.1 VBUS Divider
        2. 6.3.4.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 EPR Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 Dead Battery Operation
        3. 7.2.2.3 CC Line Capacitance
        4. 7.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 7.2.2.5 FLT Pin Operation
        6. 7.2.2.6 How to Connect Unused Pins
      3. 7.2.3 EPR Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     52

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Device Functional Modes

Table 6-3 describes all of the functional modes for the TPD4S480. The "X" in the below table are "don't care" conditions, meaning any value can be present within the absolute maximum ratings of the data sheet and maintain that functional mode.

Table 6-3 Device Mode Table
Device Mode Table Inputs Outputs
MODE VPWR C_CCx C_SBUx RPD_Gx TJ FLT CC FETs SBU FETs VBUS_LV EPR_BLK_G
Normal Operating Conditions Unpowered, no dead battery support <UVLO X X Grounded X High-Z OFF OFF VBUS Disabled
Unpowered, dead battery support <UVLO X X Shorted to C_CCx X High-Z OFF OFF VBUS Disabled
Powered on, SPR mode >UVLO <OVP <OVP X, forced OFF <TSD High-Z ON ON VBUS Enabled
Powered on, EPR mode >UVLO <OVP <OVP X, forced OFF <TSD High-Z ON ON Divided VBUS Disabled
Fault Conditions Thermal shutdown >UVLO X X X, forced OFF >TSD Low (Fault Asserted) OFF OFF Maintains EPR state Maintains EPR state
CC over voltage condition >UVLO >OVP X X, forced OFF <TSD Low (Fault Asserted) OFF OFF Maintains EPR state Maintains EPR state
SBU over voltage condition >UVLO X >OVP X, forced OFF <TSD Low (Fault Asserted) OFF OFF Maintains EPR state Maintains EPR state
IEC ESD generated over voltage condition(1) >UVLO X X RD ON if RPD_Gx is shorted to C_CCx <TSD Low (Fault Asserted) OFF OFF Maintains current EPR state Maintains current EPR state
(1) This row describes the state of the device while still in OVP after the IEC ESD strike which put the device into OVP is over, and the voltages on the C_CCx and C_SBUx pins have returned to their normal voltage levels.