JAJSP20 November   2024 TPD4S480

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—IEC Specification
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63-VDC Tolerant
      2. 6.3.2 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      3. 6.3.3 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      4. 6.3.4 EPR Adapter
        1. 6.3.4.1 VBUS Divider
        2. 6.3.4.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 EPR Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 Dead Battery Operation
        3. 7.2.2.3 CC Line Capacitance
        4. 7.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 7.2.2.5 FLT Pin Operation
        6. 7.2.2.6 How to Connect Unused Pins
      3. 7.2.3 EPR Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
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パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VI Input voltage VPWR 2.7 3.3 4.5 V
RPD_G1, RPD_G2 0 5.5 V
EPR_EN 0 VPWR V
VBUS 0 51 V
VO Output voltage FLT Pull-up resistor power rail 2.7 5.5 V
VIO I/O voltage CC1, CC2, C_CC1, C_CC2 0 5.5 V
SBU1, SBU2, C_SBU1, C_SBU2 0 4.3 V
IVCONN VCONN Current Current flowing into CC1/2 and flowing out of C_CC1/2, TJ ≤ 105 ℃ 600 mA
IVCONN VCONN Current Current flowing into CC1/2 and flowing out of C_CC1/2,  TJ ≤ 85 ℃ 1.25 A
TJ Operating Junction Temperature -40 125 ℃
External Components(1) External Components(1) FLT Pull-up resistance 1.7 300 kΩ
VBIAS capacitance (2) 0.04 0.1 0.14 µF
VPWR Capacitance 0.3 1 µF
VBUS_LV Capacitance 0.1 µF
(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented should be within the minimum and maximums listed in the table.
(2) The VBIAS pin requires a minimum 63-VDC rated capacitor. A 100-VDC rated capacitor is recommended to reduce capacitance derating.
See the VBIAS Capacitor Selection section for more information on selecting the VBIAS capacitor.